PIC16F87XA
DS39582B-page 190
2003 Microchip Technology Inc.
TABLE 17-9:
SPI MODE REQUIREMENTS
FIGURE 17-15:
I2C BUS START/STOP BITS TIMING
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
70*
TSSL2SCH,
TSSL2SCL
SS
↓ to SCK ↓ or SCK ↑ Input
TCY
——
ns
71*
TSCH
SCK Input High Time (Slave mode)
TCY + 20
—
ns
72*
TSCL
SCK Input Low Time (Slave mode)
TCY + 20
—
ns
73*
TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge
100
—
ns
74*
TSCH2DIL,
TSCL2DIL
Hold Time of SDI Data Input to SCK Edge
100
—
ns
75*
TDOR
SDO Data Output Rise Time
Standard(F)
Extended(LF)
—
10
25
50
ns
76*
TDOF
SDO Data Output Fall Time
—
10
25
ns
77*
TSSH2DOZSS
↑ to SDO Output High-Impedance
10
—
50
ns
78*
TSCR
SCK Output Rise Time
(Master mode)
Standard(F)
Extended(LF)
—
10
25
50
ns
79*
TSCF
SCK Output Fall Time (Master mode)
—
10
25
ns
80*
TSCH2DOV,
TSCL2DOV
SDO Data Output Valid after
SCK Edge
Standard(F)
Extended(LF)
—
50
145
ns
81*
TDOV2SCH,
TDOV2SCL
SDO Data Output Setup to SCK Edge
TCY
——
ns
82*
TSSL2DOV
SDO Data Output Valid after SS
↓ Edge
—
50
ns
83*
TSCH2SSH,
TSCL2SSH
SS
↑ after SCK Edge
1.5 TCY + 40
—
ns
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
91
93
SCL
SDA
Start
Condition
Stop
Condition
90
92