參數(shù)資料
型號(hào): PIC16LF877-04I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 184/218頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX14 44TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 14KB(8K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 368 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
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PIC16F87X
DS30292C-page 66
2001 Microchip Technology Inc.
REGISTER 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
R/W-0
R-0
SMP
CKE
D/A
PS
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in slave mode
In I2C Master or Slave mode:
1
= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0
= Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3 and Figure 9-4)
SPI mode:
For CKP = 0
1
= Data transmitted on rising edge of SCK
0
= Data transmitted on falling edge of SCK
For CKP = 1
1
= Data transmitted on falling edge of SCK
0
= Data transmitted on rising edge of SCK
In I2C Master or Slave mode:
1
= Input levels conform to SMBus spec
0
= Input levels conform to I2C specs
bit 5
D/A: Data/Address bit (I2C mode only)
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
bit 4
P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1
= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0
= STOP bit was not detected last
bit 3
S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1
= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0
= START bit was not detected last
bit 2
R/W: Read/Write bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit or not ACK bit.
In I2C Slave mode:
1
= Read
0
= Write
In I2C Master mode:
1
= Transmit is in progress
0
= Transmit is not in progress
Logical OR of this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
bit 1
UA: Update Address (10-bit I2C mode only)
1
= Indicates that the user needs to update the address in the SSPADD register
0
= Address does not need to be updated
bit
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1
= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0
= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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