參數(shù)資料
型號(hào): PIC16LF77T-I/PTG
廠商: Microchip Technology
文件頁(yè)數(shù): 33/104頁(yè)
文件大小: 0K
描述: IC MCU FLASH 8KX14 44TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 14KB(8K x 14)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 368 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 帶卷 (TR)
PIC16F7X
DS30325B-page 24
2002 Microchip Technology Inc.
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt.
REGISTER 2-6:
PIE2 REGISTER (ADDRESS 8Dh)
2.2.2.7
PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt.
REGISTER 2-7:
PIR2 REGISTER (ADDRESS 0Dh)
U-0
R/W-0
CCP2IE
bit 7
bit 0
bit 7-1
Unimplemented: Read as '0'
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1
= Enables the CCP2 interrupt
0
= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0
R/W-0
CCP2IF
bit 7
bit 0
bit 7-1
Unimplemented: Read as '0'
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare mode:
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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