參數(shù)資料
型號: PIC16LF73T-I/SO
廠商: Microchip Technology
文件頁數(shù): 67/104頁
文件大?。?/td> 0K
描述: IC MCU FLASH 4KX14 A/D 28SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標準包裝: 1,600
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
其它名稱: PIC16LF73TI/SO
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
57
M9999-030210-1.0
Receive Control Register 1 (0x74 – 0x75): RXCR1 (Continued)
Bit
Default Value
R/W
Description
7
0x0
RW
RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast frames.
6
0x0
RW
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including broadcast
frames).
5
0x0
RW
RXUE Receive Unicast Enable
When this bit is set, the RX module receives unicast frames that match the 48-bit Station
MAC address of the module.
4
0x0
RW
RXAE Receive All Enable
When this bit is set, the KSZ8851-16MLLJ receives all incoming frames, regardless of the
frame’s destination address (see Address Filtering Scheme in Table 3 for detail).
3
0x0
RW
Reserved
2
0x0
RW
Reserved
1
0x0
RW
RXINVF Receive Inverse Filtering
When this bit is set, the KSZ8851-16MLLJ receives function with address check operation
in inverse filtering mode (see Address Filtering Scheme in Table 3 for detail).
0
0x0
RW
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state.
When this bit is cleared, the receive process is placed in the stopped state upon
completing reception of the current frame.
Receive Control Register 2 (0x76 – 0x77): RXCR2
This register holds control information programmed by the CPU to control the receive function.
Bit
Default Value
R/W
Description
15-5
-
RO
Reserved.
4
0x0
RW
IUFFP IPV4/IPV6/UDP Fragment Frame Pass
When this bit is set, the KSZ8851-16MLLJ will pass the checksum check at receive side
for IPv4/IPv6 UDP frame with fragment extension header.
When this bit is cleared, the KSZ8851-16MLLJ will perform checksum operation based on
configuration and doesn’t care whether it’s a fragment frame or not.
3
0x0
RW
RXIUFCEZ Receive IPV4/IPV6/UDP Frame Checksum Equal Zero
When this bit is set, the KSZ8851-16MLLJ will pass the filtering for IPv4/IPv6 UDP frame
with UDP checksum equal to zero.
When this bit is cleared, the KSZ8851-16MLLJ will drop IPv4/IPv6 UDP packet with UDP
checksum equal to zero.
2
0x1
RW
UDPLFE UDP Lite Frame Enable
When this bit is set, the KSZ8851-16MLLJ will check the checksum at receive side and
generate the checksum at transmit side for UDP Lite frame.
When this bit is cleared, the KSZ8851-16MLLJ will pass the checksum check at receive
side and skip the checksum generation at transmit side for UDP Lite frame.
1
0x0
RW
RXICMPFCC Receive ICMP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct ICMP checksum for incoming
ICMP frames (only for non-fragment frame). Any received ICMP frames with incorrect
checksum will be discarded.
0
0x0
RW
RXSAF Receive Source Address Filtering
When this bit is set, the KSZ8851-16MLLJ will drop the frame if the source address is
same as MAC address in MARL, MARM, MARH registers.
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