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2010-2012 Microchip Technology Inc.
DS41417B-page 137
PIC16(L)F722A/723A
FIGURE 16-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 16-1:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
TXREG
AUSART Transmit Data Register
0000 0000
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
Legend:
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX/CK pin
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0
bit 1
bit 7/8
bit 0
Note:
This timing diagram shows two consecutive transmissions.
1 TCY
TXIF bit
(Transmit Buffer
Empty Flag)