
2010-2012 Microchip Technology Inc.
DS41417B-page 187
PIC16(L)F722A/723A
21.2
Instruction Descriptions
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
k
Operands:
0
k 255
Operation:
(W) + k
(W)
Status Affected:
C, DC, Z
Description:
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the
W register.
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
f,d
Operands:
0
f 127
d
0,1
Operation:
(W) + (f)
(destination)
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW
AND literal with W
Syntax:
[ label ] ANDLW
k
Operands:
0
k 255
Operation:
(W) .AND. (k)
(W)
Status Affected:
Z
Description:
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
f,d
Operands:
0
f 127
d
0,1
Operation:
(W) .AND. (f)
(destination)
Status Affected:
Z
Description:
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
BCF
Bit Clear f
Syntax:
[ label ] BCF
f,b
Operands:
0
f 127
0
b 7
Operation:
0 (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0
f 127
0
b 7
Operation:
1 (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
Operands:
0
f 127
0
b 7
Operation:
skip if (f<b>) = 0
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2-cycle instruction.