參數(shù)資料
型號： PIC16LF721-I/ML
廠商： Microchip Technology
文件頁數(shù)： 58/135頁
文件大小： 0K
描述： MCU PIC 4K FLASH 20-QFN
產(chǎn)品培訓模塊： 8-bit PIC® Microcontroller Portfolio
標準包裝： 91
系列： PIC® XLP™ 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 16MHz
連通性： I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 17
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-VFQFN 裸露焊盤
包裝： 管件
2010-2011 Microchip Technology Inc.
Preliminary
DS41430C-page 29
PIC16(L)F720/721
3.1
MCLR
The PIC16(L)F720/721 has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a Reset does not drive the
MCLR pin low.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 3-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RA3/MCLR pin
becomes an external Reset input. In this mode, the
RA3/MCLR pin has a weak pull-up to VDD. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
FIGURE 3-2:
RECOMMENDED MCLR
CIRCUIT
3.2
Power-on Reset (POR)
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum rise time for VDD is required. See
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until VDD reaches VBOR (see Section 3.5
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
3.3
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the WDT
oscillator. For more information, see Section 7.3
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or pro-
grammed) the Power-up Timer. The Power-up Timer
should be enabled when Brown-out Reset is enabled,
although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
VDD variation
Temperature variation
Process variation
See DC
parameters for details (Section 23.0
3.4
Watchdog Timer (WDT)
The WDT has the following features:
Shares an 8-bit prescaler with Timer0
Time-out period is from 17 ms to 2.2 seconds,
nominal
Enabled by a Configuration bit
WDT is cleared under certain conditions described in
3.4.1
WDT OSCILLATOR
The WDT derives its time base from 31 kHz internal
oscillator.
VDD
PIC MCU
MCLR
R1
10 k
C1
0.1
F
Note:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
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