SSP I2C Mode Operation
參數(shù)資料
型號： PIC16LF72-I/ML
廠商： Microchip Technology
文件頁數(shù)： 83/136頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 2KX14 28QFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 61
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 3.5KB（2K x 14）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-VQFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁面： 639 (CN2011-ZH PDF)
PIC16F72
DS39597C-page 48
2007 Microchip Technology Inc.
9.3
SSP I2C Mode Operation
The SSP module in I2C mode fully implements all slave
functions, except general call support and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementations of the master func-
tions. The SSP module implements the Standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 9-5:
SSP BLOCK DIAGRAM
(I2C MODE)
The SSP module has five registers for I2C operation:
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly
accessible
SSP Address Register (SSPADD)
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
I2C Slave mode (7-bit address)
I2C Slave mode (10-bit address)
I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
I2C Firmware controlled Master operation, Slave
is IDLE
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
Additional information on SSP I2C operation may be
found in the PIC Mid-Range MCU Reference Manual
(DS33023).
9.3.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
Either or both of the following conditions will cause the
SSP module not to give this ACK pulse.
a)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b)
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 9-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the SSP
module are shown in timing parameter #100 and
parameter #101.
9.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the eight bits are shifted into the SSPSR register.
All incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
The SSPSR register value is loaded into the
SSPBUF register.
b)
The buffer full bit, BF is set.
c)
An ACK pulse is generated.
d)
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated, if enabled) - on the falling
edge of the ninth SCL pulse.
Read
Write
SSPSR Reg
Match Detect
SSPADD Reg
START and
STOP Bit Detect
SSPBUF Reg
Internal
Data Bus
Addr Match
Set, RESET
S, P Bits
(SSPSTAT Reg)
RC3/SCK/SCL
RC4/
Shift
Clock
MSb
SDI/
LSb
SDA
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參數(shù)描述
PIC16LF72ISS 制造商:MICROCHIP 功能描述:New
PIC16LF72T-I/ML 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16LF72T-I/MLG 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O Lead Free Package RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16LF72T-I/SO 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16LF72T-I/SOG 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O Lead Free Package RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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