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    參數(shù)資料
    型號(hào): PIC16LF1934-I/PT
    廠商: Microchip Technology
    文件頁(yè)數(shù): 10/92頁(yè)
    文件大?。?/td> 0K
    描述: IC PIC MCU FLASH 256KX7 44-TQFP
    產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
    8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝: 160
    系列: PIC® XLP™ 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 32MHz
    連通性: I²C,LIN,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,POR,PWM,WDT
    輸入/輸出數(shù): 36
    程序存儲(chǔ)器容量: 7KB(4K x 14)
    程序存儲(chǔ)器類型: 閃存
    EEPROM 大小: 256 x 8
    RAM 容量: 256 x 8
    電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 14x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 44-TQFP
    包裝: 托盤(pán)
    產(chǎn)品目錄頁(yè)面: 655 (CN2011-ZH PDF)
    2009 Microchip Technology Inc.
    DS39637D-page 127
    PIC18F2480/2580/4480/4580
    10.3
    PIE Registers
    The PIE registers contain the individual enable bits for
    the peripheral interrupts. Due to the number of
    peripheral interrupt sources, there are two Peripheral
    Interrupt Enable registers (PIE1, PIE2). When IPEN = 0,
    the PEIE bit must be set to enable any of these
    peripheral interrupts.
    REGISTER 10-7:
    PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
    R/W-0
    PSPIE(1)
    ADIE
    RCIE
    TXIE
    SSPIE
    CCP1IE
    TMR2IE
    TMR1IE
    bit 7
    bit 0
    Legend:
    R = Readable bit
    W = Writable bit
    U = Unimplemented bit, read as ‘0’
    -n = Value at POR
    ‘1’ = Bit is set
    ‘0’ = Bit is cleared
    x = Bit is unknown
    bit 7
    PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
    1 = Enables the PSP read/write interrupt
    0 = Disables the PSP read/write interrupt
    bit 6
    ADIE: A/D Converter Interrupt Enable bit
    1 = Enables the A/D interrupt
    0 = Disables the A/D interrupt
    bit 5
    RCIE: EUSART Receive Interrupt Enable bit
    1 = Enables the EUSART receive interrupt
    0 = Disables the EUSART receive interrupt
    bit 4
    TXIE: EUSART Transmit Interrupt Enable bit
    1 = Enables the EUSART transmit interrupt
    0 = Disables the EUSART transmit interrupt
    bit 3
    SSPIE: Master Synchronous Serial Port Interrupt Enable bit
    1 = Enables the MSSP interrupt
    0 = Disables the MSSP interrupt
    bit 2
    CCP1IE: CCP1 Interrupt Enable bit
    1 = Enables the CCP1 interrupt
    0 = Disables the CCP1 interrupt
    bit 1
    TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
    1 = Enables the TMR2 to PR2 match interrupt
    0 = Disables the TMR2 to PR2 match interrupt
    bit 0
    TMR1IE: TMR1 Overflow Interrupt Enable bit
    1 = Enables the TMR1 overflow interrupt
    0 = Disables the TMR1 overflow interrupt
    Note 1:
    This bit is reserved on PIC18F2X80 devices; always maintain this bit clear.
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