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  • 參數(shù)資料
    型號: PIC16LF1828-E/SS
    廠商: Microchip Technology
    文件頁數(shù): 63/101頁
    文件大?。?/td> 0K
    描述: IC MCU 8BIT 7KB FLASH 20SSOP
    標(biāo)準(zhǔn)包裝: 67
    系列: PIC® XLP™ mTouch™ 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 32MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 17
    程序存儲器容量: 7KB(4K x 14)
    程序存儲器類型: 閃存
    EEPROM 大?。?/td> 256 x 8
    RAM 容量: 256 x 8
    電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 125°C
    封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
    包裝: 管件
    204
    2552K–AVR–04/11
    ATmega329/3290/649/6490
    A counter overflow interrupt will wake up the processor from Idle sleep mode.
    Bit 5 – USIPF: Stop Condition Flag
    When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected.
    The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is
    useful when implementing Two-wire bus master arbitration.
    Bit 4 – USIDC: Data Output Collision
    This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag
    is only valid when Two-wire mode is used. This signal is useful when implementing Two-wire
    bus master arbitration.
    Bits 3..0 – USICNT3..0: Counter Value
    These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or
    written by the CPU.
    The 4-bit counter increments by one for each clock generated either by the external clock edge
    detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe
    bits. The clock source depends of the setting of the USICS1..0 bits. For external clock operation
    a special feature is added that allows the clock to be generated by writing to the USITC strobe
    bit. This feature is enabled by write a one to the USICLK bit while setting an external clock
    source (USICS1 = 1).
    Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
    (USCK/SCL) are can still be used by the counter.
    20.5.3
    USICR – USI Control Register
    The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
    and clock strobe.
    Bit 7 – USISIE: Start Condition Interrupt Enable
    Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-
    rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be
    executed. Refer to the USISIF bit description on page 203 for further details.
    Bit 6 – USIOIE: Counter Overflow Interrupt Enable
    Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when
    the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.
    Refer to the USIOIF bit description on page 203 for further details.
    Bit 5..4 – USIWM1..0: Wire Mode
    These bits set the type of wire mode to be used. Basically only the function of the outputs are
    affected by these bits. Data and clock inputs are not affected by the mode selected and will
    always have the same function. The counter and Shift Register can therefore be clocked exter-
    nally, and data input sampled, even when outputs are disabled. The relations between
    USIWM1..0 and the USI operation is summarized in Table 20-1.
    Bit
    7
    6
    5
    4
    3
    2
    1
    0
    USISIE
    USIOIE
    USIWM1
    USIWM0
    USICS1
    USICS0
    USICLK
    USITC
    USICR
    Read/Write
    R/W
    W
    Initial Value
    0
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