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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC16LF1826T-I/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/109闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | MCU 8BIT 2K FLASH 20SSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1,600 |
| 绯诲垪锛� | PIC® XLP™ mTouch™ 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 32MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 16 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 256 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 12x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 20-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 甯跺嵎 (TR) |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�鐣�(d膩ng)鍓嶇5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�
2011 Microchip Technology Inc.
DS41391D-page 13
PIC16(L)F1826/27
RB3/AN9/CPS9/MDOUT/
CCP1(1,3)/P1A(1,3)
RB3
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN9
AN
鈥�
A/D Channel 9 input.
CPS9
AN
鈥�
Capacitive sensing input 9.
MDOUT
鈥�
CMOS Modulator output.
CCP1
ST
CMOS Capture/Compare/PWM1.
P1A
鈥�
CMOS PWM output.
RB4/AN8/CPS8/SCL1/SCK1/
MDCIN2
RB4
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN8
AN
鈥�
A/D Channel 8 input.
CPS8
AN
鈥�
Capacitive sensing input 8.
SCL1
I2C
OD
I2C clock 1.
SCK1
ST
CMOS SPI clock 1.
MDCIN2
ST
鈥�
Modulator Carrier Input 2.
RB5/AN7/CPS7/P1B/TX(1)/CK(1)/
SCL2(2)/SCK2(2)/SS1(1,3)
RB5
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN7
AN
鈥�
A/D Channel 7 input.
CPS7
AN
鈥�
Capacitive sensing input 7.
P1B
鈥�
CMOS PWM output.
TX
鈥�
CMOS USART asynchronous transmit.
CK
ST
CMOS USART synchronous clock.
SCL2
I2C
OD
I2C clock 2.
SCK2
ST
CMOS SPI clock 2.
SS1
ST
鈥�
Slave Select input 1.
RB6/AN5/CPS5/T1CKI/T1OSI/
P1C(1,3)/CCP2(1,2,3)/P2A(1,2,3)/
ICSPCLK
RB6
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN5
AN
鈥�
A/D Channel 5 input.
CPS5
AN
鈥�
Capacitive sensing input 5.
T1CKI
ST
鈥�
Timer1 clock input.
T1OSO
XTAL
Timer1 oscillator connection.
P1C
鈥�
CMOS PWM output.
CCP2
ST
CMOS Capture/Compare/PWM2.
P2A
鈥�
CMOS PWM output.
ICSPCLK
ST
鈥�
Serial Programming Clock.
RB7/AN6/CPS6/T1OSO/
P1D(1,3)/P2B(1,2,3)/MDCIN1/
ICSPDAT
RB7
TTL
CMOS General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
AN6
AN
鈥�
A/D Channel 6 input.
CPS6
AN
鈥�
Capacitive sensing input 6.
T1OSO
XTAL
Timer1 oscillator connection.
P1D
鈥�
CMOS PWM output.
P2B
鈥�
CMOS PWM output.
MDCIN1
ST
鈥�
Modulator Carrier Input 1.
ICSPDAT
ST
CMOS ICSP Data I/O.
TABLE 1-2:
PIC16(L)F1826/27 PINOUT DESCRIPTION (CONTINUED)
Name
Function
Input
Type
Output
Type
Description
Legend:
AN = Analog input or output CMOS= CMOS compatible input or output
OD
= Open Drain
TTL = TTL compatible input
ST
= Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1:
Pin functions can be moved using the APFCON0 or APFCON1 register.
2:
Functions are only available on the PIC16(L)F1827.
3:
Default function location.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| D38999/26KJ19PN | CONN PLUG 19POS STRAIGHT W/PINS |
| PIC16F1826T-I/SS | IC PIC MCU FLASH 3.5KB 20-SSOP |
| D38999/26WJ7SC | CONN PLUG 99POS STRAIGHT W/SCKT |
| MRF1.6/5.6-PJ-59U | CONN JACK PANEL STR RG-59U |
| GRM2165C1H820JZ01J | CAP CER 82PF 50V 5% NP0 0805 |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| PIC16LF1827-E/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 18P 7 KB Flash 384B RAM 32 MHz Int Osc RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16LF1827-E/MV | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 7KB Flash 384B RAM RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16LF1827-E/P | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 18P 7 KB Flash 384B RAM 32 MHz Int Osc RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16LF1827-E/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 18P 7 KB Flash 384B RAM 32 MHz Int Osc RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16LF1827-E/SS | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 18P 7 KB Flash 384B RAM 32 MHz Int Osc RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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