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203
ATmega8515(L)
2512K–AVR–01/10
Table 100. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/tCLCL
Oscillator Frequency
0.0
16
MHz
10
t
RLDV
Read Low to Data Valid
325
3.0t
CLCL-50
ns
12
tRLRH
RD Pulse Width
365
3.0tCLCL-10
ns
15
tDVWH
Data Valid to WR High
375
3.0tCLCL
ns
16
t
WLWH
WR Pulse Width
365
3.0t
CLCL-10
ns
Table 101. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/tCLCL
Oscillator Frequency
0.0
16
MHz
10
tRLDV
Read Low to Data Valid
325
3.0tCLCL-50
ns
12
t
RLRH
RD Pulse Width
365
3.0t
CLCL-10
ns
14
tWHDX
Data Hold After WR High
240
2.0tCLCL-10
ns
15
tDVWH
Data Valid to WR High
375
3.0tCLCL
ns
16
t
WLWH
WR Pulse Width
365
3.0t
CLCL-10
ns
Table 102. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/tCLCL
Oscillator Frequency
0.0
8
MHz
1t
LHLL
ALE Pulse Width
235
t
CLCL-15
ns
2t
AVLL
Address Valid A to ALE Low
115
0.5t
ns
3a
t
LLAX_ST
Address Hold After ALE Low,
write access
55
ns
3b
tLLAX_LD
Address Hold after ALE Low,
read access
55
ns
4t
AVLLC
Address Valid C to ALE Low
115
0.5t
ns
5t
AVRL
Address Valid to RD Low
235
1.0t
CLCL-15
ns
6tAVWL
Address Valid to WR Low
235
1.0tCLCL-15
ns
7t
LLWL
ALE Low to WR Low
115
130
0.5t
0.5t
CLCL+5
ns
8tLLRL
ALE Low to RD Low
115
130
0.5tCLCL+5
ns
9
tDVRH
Data Setup to RD High
45
ns
10
t
RLDV
Read Low to Data Valid
1901.0t
CLCL-60
ns
11
tRHDX
Data Hold After RD High
0
ns