2009 Microchip Technology Inc.
DS39632E-page 219
PIC18F2455/2550/4455/4550
FIGURE 19-12:
I2C SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001
(RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SS
PI
F
(
P
IR
1
<
3
>
)
BF
(
S
SPS
TA
T
<
0
>
)
S
1
2
3
4
56
7
8
9
1
2
3
4
5
6
7
89
1
2
3
4
5
7
8
9
P
1
0
A
9
A
8
A
7
A
6
A
5
X
A
3
A2
X
D7
D6
D5
D4
D3
D1
D
0
Re
ce
iv
eDa
ta
Byte
ACK
R/W
=
0
ACK
Re
ceive
F
irs
tB
yte
of
A
d
dr
ess
C
le
a
re
din
so
ftwa
re
D2
6
Cle
a
re
d
in
so
ftw
ar
e
R
e
ce
iv
eS
econd
B
yte
of
A
ddre
ss
C
lea
re
db
yh
a
rd
w
a
re
w
he
n
SSP
AD
D
is
u
p
d
a
te
d
w
ith
lo
w
byte
of
add
ress
UA
(
S
PST
A
T
<1
>)
Cl
ock
is
h
e
ld
lo
w
u
n
til
updat
e
of
S
P
A
D
has
ta
ken
pl
ac
e
UA
is
set
indicat
in
g
tha
t
the
S
P
A
D
need
sto
be
upda
ted
U
A
is
set
in
di
cati
ng
that
S
P
A
D
need
sto
be
update
d
C
le
ar
ed
by
har
d
w
a
re
w
hen
SSP
ADD
is
u
p
d
ate
d
with
h
ig
h
by
te
of
addr
e
ss
S
SPB
UF
is
wr
itte
nwith
conten
ts
o
fS
S
P
S
R
D
ummy
read
of
S
P
B
U
F
to
clear
B
F
flag
AC
K
CKP
12
3
4
5
7
8
9
D7
D6
D5
D4
D3
D1
D0
Re
ce
ive
Da
ta
B
yte
B
us
m
a
ste
r
term
inates
tran
sfer
D2
6
ACK
Cle
a
re
d
in
so
ftwa
re
Cle
a
re
d
in
so
ftwa
re
SS
PO
V
(
SSP
CO
N1
<6
>)
S
SPO
V
is
s
et
because
S
P
B
U
F
is
stil
lf
u
ll.
AC
K
is
no
tsent.
(C
K
P
do
es
not
reset
to
‘0
’w
hen
S
E
N
=
0
)
Clo
ck
is
h
e
ld
lo
w
u
n
til
upda
te
of
S
P
A
D
has
ta
ke
n
pl
ac
e
No
te
1:
x
=
Do
n’t
c
are
(i.e
.,a
dd
ress
bit
c
an
b
ee
ithe
ra
‘1
’or
a
‘0
’)
.
2:
In
th
is
ex
am
pl
e
,a
n
a
d
dr
ess
e
qu
a
lto
A9
.A8
.A
7
.A6
.A5
.X.A3
.A2
.X.X
will
b
e
Ackn
o
wl
ed
g
ed
a
nd
ca
us
ea
ni
n
te
rr
u
pt.
3:
N
ot
eth
at
the
Mo
st
S
ign
ifi
can
tbi
ts
of
the
ad
dre
ss
a
re
not
af
fe
cted
by
the
bi
t
mas
ki
ng.