
2009 Microchip Technology Inc.
DS39632E-page 241
PIC18F2455/2550/4455/4550
TABLE 19-4:
REGISTERS ASSOCIATED WITH I2C OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
SPPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
SPPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
IPR1
SPPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
PIR2
OSCFIF
CMIF
USBIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
PIE2
OSCFIE
CMIE
USBIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
IPR2
OSCFIP
CMIP
USBIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
TRISC
TRISC7
TRISC6
—
TRISC2
TRISC1
TRISC0
TRISD(1)
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
SSPBUF
MSSP Receive Buffer/Transmit Register
SSPADD
MSSP Address Register in I2C Slave mode.
MSSP Baud Rate Reload Register in I2C Master mode.
TMR2
Timer2 Register
PR2
Timer2 Period Register
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in I2C mode.
Note 1: These registers or bits are not implemented in 28-pin devices.