參數(shù)資料
型號: PIC16LC923-04I/PT
廠商: Microchip Technology
文件頁數(shù): 36/115頁
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 LCD DVR 64TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C,SPI
外圍設(shè)備: LCD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
1997 Microchip Technology Inc.
DS30444E - page 27
PIC16C9XX
4.2.2.5
PIR1 REGISTER
This register contains the individual ag bits for the
peripheral interrupts.
Note:
Interrupt ag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt ag bits are clear prior to enabling an
interrupt.
FIGURE 4-7:
PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
U-0
R/W-0
LCDIF
ADIF(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7:
LCDIF: LCD Interrupt Flag bit
1 = LCD interrupt occurred (must be cleared in software)
0 = LCD interrupt did not occur
bit 6:
ADIF: A/D Converter Interrupt Flag bit(1)
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4: Unimplemented: Read as '0'
bit 3:
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overow Interrupt Flag bit
1 = TMR1 register overowed (must be cleared in software)
0 = TMR1 register did not overow
Note 1: Bit ADIF is reserved on the PIC16C923, always maintain this bit clear.
Interrupt ag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ag bits are clear prior to
enabling an interrupt.
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