參數(shù)資料
型號: PIC16LC7X-16PTL16
廠商: Microchip Technology Inc.
英文描述: 8-Bit CMOS Microcontrollers with A/D Converter
中文描述: 8位CMOS微控制器與A / D轉(zhuǎn)換器
文件頁數(shù): 23/41頁
文件大小: 322K
代理商: PIC16LC7X-16PTL16
PIC16LC74B-16/PTL16
1999 Microchip Technology Inc.
Preliminary
DS30026A-page 23
FIGURE 2-15: I
2
C BUS DATA TIMING
TABLE 2-13:
I
2
C BUS DATA REQUIREMENTS
Parameter
No.
100*
Sym
Characteristic
Min
Max
Units
Conditions
T
HIGH
Clock high time
100 kHz mode
4.0
μ
s
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
400 kHz mode
0.6
μ
s
SSP Module
100 kHz mode
1.5T
CY
4.7
101*
T
LOW
Clock low time
μ
s
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
400 kHz mode
1.3
μ
s
SSP Module
100 kHz mode
400 kHz mode
1.5T
CY
20 + 0.1Cb
102*
T
R
SDA and SCL rise
time
1000
300
ns
ns
Cb is specified to be from
10-400 pF
103*
T
F
SDA and SCL fall time
100 kHz mode
400 kHz mode
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
90*
T
SU
:
STA
START condition
setup time
START condition hold
time
Data input hold time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
4.7
1.3
0.9
3500
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
ns
μ
s
μ
s
ns
ns
μ
s
μ
s
91*
T
HD
:
STA
106*
T
HD
:
DAT
107*
T
SU
:
DAT
Data input setup time
Note 2
92*
T
SU
:
STO
STOP condition setup
time
Output valid from
clock
Bus free time
109*
T
AA
Note 1
110*
T
BUF
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
400
pF
*
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I
2
C-bus device can be used in a standard-mode (100 kHz) I
2
C-bus system, but the requirement
Tsu:DAT
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line T
R
max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
2
C bus specification) before the SCL line
is released.
Note 1:
2:
Note:
Refer to Figure 2-2 for load conditions.
90
91
92
100
101
103
106
107
109
109
110
102
SCL
SDA
In
SDA
Out
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