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| 型號： | PIC16LC74B-16 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Bit CMOS Microcontrollers with A/D Converter |
| 中文描述： | 8位CMOS微控制器與A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/41頁 |
| 文件大?。?/td> | 322K |
| 代理商： | PIC16LC74B-16 |
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PIC16LC74B-16/PTL16
1999 Microchip Technology Inc.
Preliminary
DS30026A-page 7
2.1
DC Characteristics:
PIC16LC74B-16/PTL-04 (Commercial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C
≤
T
A
≤
Min
Typ
Max
Units
+70°C
for commercial
Conditions
Param
No.
D001
Sym
Characteristic
V
DD
Supply Voltage
2.5
V
BOR
*
-
-
-
5.5
5.5
-
V
V
V
RC, LP, XT, HS osc modes (DC - 4 MHz)
BOR enabled (Note 7)
D002*
V
DR
RAM Data Retention
Voltage
(Note 1)
V
DD
Start Voltage
to
ensure internal
Power-on Reset signal
V
DD
Rise Rate
to
ensure internal
Power-on Reset signal
Brown-out Reset
voltage trip point
Supply Current
(Note 2, 5)
TBD
D003
V
POR
-
V
SS
-
V
D004*
D004A*
S
VDD
0.05
TBD
-
-
-
-
V/mS
V/mS
PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
D005
V
BOR
3.65
-
4.35
V
BODEN bit set
D010
D010A
I
DD
-
-
-
2.0
3.0
22.5
3.8
6.0
48
mA
mA
μ
A
XT, RC osc modes
F
OSC
= 4 MHz, V
DD
= 3.0V (Note 4)
HS oscillator mode
Fosc = 16MHz, V
DD
= 3.0V
LP osc mode
F
OSC
= 32 kHz, V
DD
= 3.0V, WDT disabled
V
DD
= 3.0V, WDT disabled, 0
°
C to +70
°
C
D021
I
PD
Power-down Current
(Note 3, 5)
Module Differential
Current
(Note 6)
Watchdog Timer
Brown-out Reset
These parameters are characterized but not tested.
Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1:
This is the limit to which V
DD
can be lowered without losing RAM data.
2:
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all I
DD
measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to V
DD
.
MCLR = V
DD
; WDT enabled/disabled as specified.
3:
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V
DD
and V
SS
.
4:
For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by
the formula Ir = V
DD
/2Rext (mA) with Rext in kOhm.
5:
Timer1 oscillator (when enabled) adds approximately 20
μ
A to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6:
The
current is the additional current consumed when this peripheral is enabled. This current should be
added to the base I
DD
or I
PD
measurement.
7:
When BOR is enabled, the device will operate correctly until the V
BOR
voltage trip point is reached.
-
0.9
5
μ
A
D022*
D022A*
I
WDT
I
BOR
-
-
6.0
350
20
425
μ
A
μ
A
WDTE bit set, V
DD
= 4.0V
BODEN bit set, V
DD
= 5.0V
*
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