• 參數(shù)資料
    型號: PIC16LC72AT-04/SO
    廠商: Microchip Technology
    文件頁數(shù): 39/120頁
    文件大?。?/td> 0K
    描述: IC MCU OTP 2KX14 A/D PWM 28SOIC
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    標(biāo)準(zhǔn)包裝: 1,600
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    連通性: I²C,SPI
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 22
    程序存儲器容量: 3.5KB(2K x 14)
    程序存儲器類型: OTP
    RAM 容量: 128 x 8
    電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
    振蕩器型: 外部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
    包裝: 帶卷 (TR)
    PIC16C62B/72A
    1999 Microchip Technology Inc.
    Preliminary
    DS35008B-page 25
    4.0
    TIMER0 MODULE
    The Timer0 module timer/counter has the following fea-
    tures:
    8-bit timer/counter
    - Read and write
    - INT on overflow
    8-bit software programmable prescaler
    INT or EXT clock select
    - EXT clock edge select
    Figure 4-1 is a simplified block diagram of the Timer0
    module.
    Additional information on timer modules is available in
    the
    PICmicro
    Mid-Range
    Reference
    Manual,
    (DS33023).
    4.1
    Timer0 Operation
    Timer0 can operate as a timer or as a counter.
    Timer mode is selected by clearing bit T0CS
    (OPTION_REG<5>). In timer mode, the Timer0 mod-
    ule will increment every instruction cycle (without pres-
    caler). If the TMR0 register is written, the increment is
    inhibited for the following two instruction cycles. The
    user can work around this by writing an adjusted value
    to the TMR0 register.
    Counter mode is selected by setting bit T0CS
    (OPTION_REG<5>). In counter mode, Timer0 will
    increment either on every rising or falling edge of pin
    RA4/T0CKI. The incrementing edge is determined by
    the
    Timer0
    Source
    Edge
    Select
    bit
    T0SE
    (OPTION_REG<4>). Clearing bit T0SE selects the ris-
    ing edge. Restrictions on the external clock input are
    discussed below.
    When an external clock input is used for Timer0, it must
    meet certain requirements. The requirements ensure
    the external clock can be synchronized with the internal
    phase clock (TOSC). Also, there is a delay in the actual
    incrementing of Timer0 after synchronization.
    Additional information on external clock requirements
    is available in the Electrical Specifications section of
    this manual, and in the PICmicro Mid-Range Refer-
    ence Manual, (DS33023).
    4.2
    Prescaler
    An 8-bit counter is available as a prescaler for the
    Timer0 module, or as a postscaler for the Watchdog
    Timer, respectively (Figure 4-2). For simplicity, this
    counter is being referred to as “prescaler” throughout
    this data sheet. There is only one prescaler available
    which is shared between the Timer0 module and the
    Watchdog Timer. A prescaler assignment for the
    Timer0 module means that there is no prescaler for the
    Watchdog Timer, and vice-versa.
    The prescaler is not readable or writable.
    The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
    determine the prescaler assignment and prescale ratio.
    Clearing bit PSA will assign the prescaler to the Timer0
    module. When the prescaler is assigned to the Timer0
    module, prescale values of 1:2, 1:4, ..., 1:256 are
    selectable.
    Setting bit PSA will assign the prescaler to the Watch-
    dog Timer (WDT). When the prescaler is assigned to
    the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
    selectable.
    When assigned to the Timer0 module, all instructions
    writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
    BSF
    1,x
    ....etc.) will clear the prescaler. When
    assigned to WDT, a CLRWDT instruction will clear the
    prescaler along with the WDT.
    FIGURE 4-1:
    TIMER0 BLOCK DIAGRAM
    Note:
    Writing to TMR0 when the prescaler is
    assigned to Timer0 will clear the prescaler
    count, but will not change the prescaler
    assignment or ratio.
    Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
    2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
    RA4/T0CKI
    T0SE
    0
    1
    0
    pin
    T0CS
    FOSC/4
    Programmable
    Prescaler
    Sync with
    Internal
    clocks
    TMR0
    PSout
    (TCY delay)
    PSout
    Data Bus
    8
    PSA
    PS2, PS1, PS0
    Set interrupt
    flag bit T0IF
    on overflow
    3
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