參數(shù)資料
型號: PIC16LC715
廠商: Microchip Technology Inc.
英文描述: 8-Bit CMOS Microcontrollers with A/D Converter
中文描述: 8位CMOS微控制器與A / D轉(zhuǎn)換器
文件頁數(shù): 40/176頁
文件大小: 803K
代理商: PIC16LC715
PIC16C71X
DS30272A-page 40
1997 Microchip Technology Inc.
7.1
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
HOLD
) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-5. The source
impedance (R
S
) and the internal sampling switch (R
SS
)
impedance directly affect the time required to charge
the capacitor C
HOLD
. The sampling switch (R
SS
)
impedance varies over the device voltage (V
DD
),
Figure 7-5. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log sources is 10 k
. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time, Equation 7-
1 may be used. This equation calculates the acquisition
time to within 1/2 LSb error is used (512 steps for the
A/D). The 1/2 LSb error is the maximum error allowed
for the A/D to meet its specified accuracy.
A/D Acquisition Requirements
EQUATION 7-1:
A/D MINIMUM CHARGING
TIME
V
HOLD
= (V
REF
- (V
REF
/512)) (1 - e
(-T
CAP
/C
HOLD
(R
IC
+ R
SS
+ R
S
))
)
Given: V
HOLD
= (V
REF
/512), for 1/2 LSb resolution
The above equation reduces to:
T
CAP
= -(51.2 pF)(1 k
+ R
SS
+ R
S
) ln(1/511)
Example 7-1 shows the calculation of the minimum
required acquisition time T
ACQ
. This calculation is
based on the following system assumptions.
C
HOLD
= 51.2 pF
Rs = 10 k
1/2 LSb error
V
DD
= 5V
Rss = 7 k
Temp (application system max.) = 50
°
C
V
HOLD
= 0 @ t = 0
EXAMPLE 7-1:
CALCULATING THE
MINIMUM REQUIRED
AQUISITION TIME
T
ACQ
= Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
T
ACQ
= 5
μ
s + T
CAP
+ [(Temp - 25
°
C)(0.05
μ
s/
°
C)]
T
CAP
= -C
HOLD
(R
IC
+ R
SS
+ R
S
) ln(1/511)
-51.2 pF (1 k
+ 7 k
+ 10 k
) ln(0.0020)
-51.2 pF (18 k
) ln(0.0020)
-0.921
μ
s (-6.2364)
5.747
μ
s
T
ACQ
= 5
μ
s + 5.747
μ
s + [(50
°
C - 25
°
C)(0.05
μ
s/
°
C)]
10.747
μ
s + 1.25
μ
s
11.997
μ
s
Note 1:
The reference voltage (V
REF
) has no
effect on the equation, since it cancels
itself out.
Note 2:
The charge holding capacitor (C
HOLD
) is
not discharged after each conversion.
Note 3:
The maximum recommended impedance
for analog sources is 10 k
. This is
required to meet the pin leakage specifi-
cation.
Note 4:
After a conversion has completed, a
2.0T
AD
delay must complete before acqui-
sition can begin again. During this time the
holding capacitor is not connected to the
selected A/D input channel.
FIGURE 7-5:
ANALOG INPUT MODEL
C
PIN
5 pF
VA
Rs
ANx
V
DD
V
T
= 0.6V
V
T
= 0.6V
I leakage
±
500 nA
R
IC
1k
Sampling
Switch
SS
R
SS
C
= DAC capacitance
= 51.2 pF
V
SS
6V
5V
4V
3V
2V
Sampling Switch
( k
)
5 6 7 8 9 10 11
V
DD
Legend C
PIN
V
T
I leakage
R
IC
SS
C
HOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
various junctions
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
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