參數(shù)資料
型號(hào)： PIC16FR63
廠商： Microchip Technology Inc.
英文描述： 8-Bit CMOS FlexROM Microcontrollers(每個(gè)I/O口有25mA驅(qū)動(dòng)/吸收電流,2路捕捉/比較/PWM的微控制器)
中文描述： 8位微控制器的CMOS FlexROM（每個(gè)的I / O口有25毫安驅(qū)動(dòng)/吸收電流，2路捕捉/比較/脈寬調(diào)制的微控制器）
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 354K
代理商： PIC16FR63
1996 Microchip Technology Inc.
Advanced Information
DS30260A-page 13
PIC16FR6X
TABLE 3-2:
PIC16FR63 SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
BOR
Value on
all other
resets
(3)
Bank 0
00h
(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
02h
(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
03h
(1)
STATUS
IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
04h
(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
05h
PORTA
—
—
PORTA Data Latch when written: PORTA pins when read
--xx xxxx
--uu uuuu
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx
uuuu uuuu
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah
(1,2)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
---0 0000
0Bh
(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
(5)
(5)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
00-- 0000
00-- 0000
0Dh
PIR2
—
—
—
—–
—
—
—
CCP2IF
---- ---0
---- ---0
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
--uu uuuu
11h
TMR2
Timer2 module’s register
0000 0000
0000 0000
12h
T2CON
—
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
xxxx xxxx
uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
xxxx xxxx
uuuu uuuu
17h
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
19h
TXREG
USART Transmit Data Register
0000 0000
0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000
0000 0000
1Bh
CCPR2L
Capture/Compare/PWM2 (LSB)
xxxx xxxx
uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM2 (MSB)
xxxx xxxx
uuuu uuuu
1Dh
CCP2CON
—
—
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
1Eh-1Fh
—
Unimplemented
—
—
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition,
-
= unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose con-
tents are transferred to the upper byte of the program counter. (PC<12:8>)
3:
Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4:
The IRP and RP1 bits are reserved on the PIC16FR63, always maintain these bits clear.
5:
PIE1<7:6> and PIR1<7:6> are reserved, always maintain these bits clear.
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