156
8008H–AVR–04/11
ATtiny48/88
15.10 Compatibility with SMBus
As with any other I
2C-compliant interface there are known compatibility issues the designer
should be aware of before connecting a TWI device to SMBus devices. For use in SMBus envi-
ronments, the following should be noted:
All I/O pins of an AVR, including those of the two-wire interface, have protection diodes to
requirements of the SMBus specifications. As a result, supply voltage mustn’t be removed
from the AVR or the protection diodes will pull the bus lines down. Power down and sleep
modes is not a problem, provided supply voltages remain.
The data hold time of the TWI is lower than specified for SMBus.
SMBus has a low speed limit, while I
2C hasn’t. As a master in an SMBus environment, the
AVR must make sure bus speed does not drop below specifications, since lower bus speeds
trigger timeouts in SMBus slaves. If the AVR is configured a slave there is a possibility of a
bus lockup, since the TWI module doesn't identify timeouts.
15.11 Register Description
15.11.1
TWBR – TWI Bit Rate Register
Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
If the TWI operates in Master mode TWBR must be set to 10, or higher.
15.11.2
TWCR – TWI Control Register
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-
cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag
Bit
7
654
32
10
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
TWBR
Read/Write
R/W
Initial Value
0
Bit
7
654
32
10
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
TWCR
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0