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閰嶇敤锛� MCP1631RD-MCC2-ND - REFERENCE DESIGN MCP1631HV
PIC16F88X
DS80302F-page 6
2009 Microchip Technology Inc.
5.
Module: MSSP (I2C Slave Mode)
When the master device wants to terminate
receiving any more data from the slave device, it
will do so by sending a NACK in response to the
last data byte received from the slave. When the
slave receives the NACK, the R/W bit of the
SSPSTAT register remains set improperly.
Work around
Use the CKP bit of the SSPCON register to
determine when the master has responded with a
NACK. The CKP bit will be clear when the
response is an ACK, and set when the response is
a NACK. The CKP bit is automatically cleared to
stretch the clock when the master responds to
received data with an ACK. This gives the slave
time to load the SSPBUF register before setting
the CKP bit to release the clock stretching. When
the master responds to received data with a NACK
the CKP bit properly remains set, and there is no
clock stretching.
Affected Silicon Revisions
PIC16F882
PIC16F883/PIC16F884
PIC16F886/PIC16F887
A0
X
A0
X
A2
X
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
SI3452-B01-GM IC POE CONTROLLER MIDSPAN 40QFN
V300C48M75BG3 CONVERTER MOD DC/DC 48V 75W
V300C48M75BG2 CONVERTER MOD DC/DC 48V 75W
SI3452A-B01-GM IC POE CONTROLLER MIDSPAN 40QFN
SI3452C-B01-GM IC POE CONTROLLER MIDSPAN 40QFN
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