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| 型號(hào)： | PIC16F877-20I/L |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 154/218頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 8KX14 EE 44PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | PIC® 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 33 |
| 程序存儲(chǔ)器容量： | 14KB（8K x 14） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 368 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線(xiàn)） |
| 包裝： | 管件 |
| 配用： | AC164309-ND - MODULE SKT FOR PM3 44PLCC 444-1001-ND - DEMO BOARD FOR PICMICRO MCU 309-1040-ND - ADAPTER 44-PLCC ZIF TO 40-DIP 309-1039-ND - ADAPTER 44-PLCC TO 40-DIP |
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PIC16F87X
DS30292C-page 38
2001 Microchip Technology Inc.
3.6
Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F873 or PIC16F876.
PORTD operates as an 8-bit wide Parallel Slave Port or
microprocessor port, when control bit PSPMODE
(TRISE<4>) is set. In Slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
The PSP can directly interface to an 8-bit microproces-
sor data bus. The external microprocessor can read or
write the PORTD latch as an 8-bit latch. Setting bit
PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (chip select) input. For this functionality, the cor-
responding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set). The
A/D
port
configuration
bits
PCFG3:PCFG0
(ADCON1<3:0>) must be set to configure pins
RE2:RE0 as digital I/O.
There are actually two 8-bit latches: one for data out-
put, and one for data input. The user writes 8-bit data
to the PORTD data latch and reads data from the port
pin latch (note that they have the same address). In this
mode, the TRISD register is ignored, since the external
device is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 3-10). The interrupt flag bit PSPIF
(PIR1<7>) is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 3-11), indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
FIGURE 3-9:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
Data Bus
WR
Port
RD
RDx
Q
D
CK
EN
QD
EN
Port
pin
One bit of PORTD
Set Interrupt Flag
PSPIF(PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
TTL
Note 1: I/O pins have protection diodes to VDD and VSS.
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