2001 Microchip Technology Inc.
DS30292C-page 81
PIC16F87X
9.2.10
I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I2C
module is in the IDLE state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the baud rate generator is loaded with the
contents of SSPADD<6:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (TBRG). When the baud rate generator
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled high
the baud rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one TBRG. This action is then
followed by assertion of the SDA pin (SDA is low) for
one TBRG, while SCL is high. Following this, the RSEN
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the baud rate generator has timed out.
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
9.2.10.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
FIGURE 9-13:
REPEAT START CONDITION WAVEFORM
Note
1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
SDA is sampled low when SCL
goes from low to high.
SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
Note:
Because
queueing
of
events
is
not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
SDA
SCL
Sr = Repeated START
Write to SSPCON2
Write to SSPBUF occurs here
Falling edge of ninth clock
End of Xmit
At completion of START bit,
hardware clears RSEN bit
1st bit
Set S (SSPSTAT<3>)
TBRG
SDA = 1,
SCL (no change)
SCL = 1
occurs here
TBRG
and sets SSPIF