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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16F876A-I/SP
寤犲晢锛� Microchip Technology
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鏂囦欢澶�?銆�?/td> 0K
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鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
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绯诲垪锛� PIC® 16F
鏍稿績铏曠悊鍣細 PIC
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绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
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RAM 瀹归噺锛� 368 x 8
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鐢�(ch菐n)鍝佺洰閷勯爜闈細 641 (CN2011-ZH PDF)
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绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�绗�173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�绗�221闋�绗�222闋�绗�223闋�绗�224闋�绗�225闋�绗�226闋�绗�227闋�绗�228闋�绗�229闋�鐣�(d膩ng)鍓嶇230闋�绗�231闋�绗�232闋�绗�233闋�绗�234闋�
2003 Microchip Technology Inc.
DS39582B-page 93
PIC16F87XA
FIGURE 9-14:
I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SD
A
SC
L
S
SPI
F
B
F
(
SSP
ST
A
T
<0
>)
S
1
2
3
4
5
6
7
8
9
1
23
4
5
6
7
89
1
2
3
4
5
7
8
9
P
1
0
A
9A
8
A
7
A
6
A
5
A
4
A
3
A
2A
1
A
0
D
7D
6D
5
D
4
D
3
D
1
D
0
Re
ce
ive
Da
ta
Byte
ACK
R/W
=
0
ACK
R
e
cei
v
e
Fi
rst
B
y
te
of
A
ddr
ess
Cle
a
re
d
in
so
ft
wa
re
D2
6
(P
IR
1<
3>
)
Cle
a
re
d
in
so
ft
wa
re
R
e
cei
v
e
S
e
cond
B
y
te
o
fA
ddre
s
C
leare
d
by
ha
rdw
a
re
w
hen
S
P
A
D
i
s
upd
ated
w
ith
l
o
w
byte
o
faddr
ess
aft
e
rfa
lli
n
g
edge
U
A
(
S
SP
S
T
A
T
<1
>)
Clo
ck
is
h
e
ld
lo
w
u
n
til
u
pdate
of
S
P
A
D
h
a
s
ta
ke
n
pl
ace
UA
is
se
tindicating
that
S
P
A
D
nee
ds
to
b
e
updat
ed
UA
is
set
indica
ting
tha
t
S
P
A
D
n
eeds
to
be
upd
ated
C
le
a
red
b
y
har
dw
are
w
h
en
S
P
A
D
is
updat
ed
w
it
h
ig
h
by
te
of
a
ddre
ss
after
fal
ling
e
dge
S
SPB
UF
is
wr
itte
n
with
conten
ts
of
S
P
S
R
Du
m
y
r
e
a
d
o
fSSP
BUF
to
clea
rB
F
fla
g
ACK
CK
P
12
3
4
5
7
8
9
D7
D6
D5
D4
D3
D1
D0
Re
ce
ive
Da
ta
B
y
te
B
u
s
m
a
ste
r
ter
m
inate
s
tra
n
sfer
D2
6
ACK
C
lea
re
d
i
n
s
o
ft
w
ar
e
Cle
a
re
d
in
so
ft
w
a
re
SSP
O
V
(
SSP
CO
N
<
6
>
)
CK
P
writte
n
to
鈥�
1
鈥�
No
te
:
A
n
updat
e
of
the
S
P
A
D
reg
ist
er
b
e
for
e
the
fal
ling
edge
o
f
th
e
ni
nth
cl
ock
will
h
a
ve
n
o
e
ffe
ct
o
n
UA,
a
n
d
UA
will
re
ma
in
set.
No
te
:
A
n
upda
te
of
the
S
P
A
D
regi
ste
r
befo
re
the
fal
ling
edg
e
o
f
th
e
n
inth
cl
ock
wil
lhave
no
e
ffect
on
UA
and
UA
will
rem
a
in
set.
in
softwar
e
Clo
ck
is
h
e
ld
lo
w
u
n
ti
l
upd
ate
of
S
P
A
D
has
ta
ken
pl
ace
of
ni
nth
cl
o
c
k
of
ni
nt
h
cl
ock
SSP
O
V
is
s
e
t
b
e
cause
S
P
B
U
F
is
still
fu
ll.
A
C
K
i
s
not
sent.
Du
m
y
r
e
a
d
o
fSSP
BUF
to
clea
rB
F
flag
Clo
ck
is
h
e
ld
lo
w
u
n
til
CK
P
is
set
to
鈥�1
鈥�
C
lo
ck
i
s
not
hel
d
l
o
w
becau
se
A
C
K
=
1
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