參數(shù)資料
型號(hào): PIC16F870-I/SP
廠商: Microchip Technology
文件頁數(shù): 112/143頁
文件大小: 0K
描述: IC MCU FLASH 2KX14 EE 28DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 639 (CN2011-ZH PDF)
配用: I3-DB16F871-ND - BOARD DAUGHTER ICEPIC3
PIC16F870/871
DS30569B-page 68
2003 Microchip Technology Inc.
9.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 9-4. The
data is received on the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter, operating at x16 times the baud
rate; whereas, the main receive serial shifter operates
at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the Receive (Serial) Shift
register (RSR). After sampling the STOP bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited,
and no further data will be received. It is therefore,
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading the RCREG register in
order not to lose the old FERR and RX9D information.
FIGURE 9-4:
USART RECEIVE BLOCK DIAGRAM
FIGURE 9-5:
ASYNCHRONOUS RECEPTION
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register
MSb
LSb
RX9D
RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
÷64
÷16
or
STOP
START
(8)
7
1
0
RX9
FOSC
START
bit
bit7/8
bit1
bit0
bit7/8
bit0
STOP
bit
START
bit
START
bit
bit7/8
STOP
bit
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
STOP
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
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