參數(shù)資料
型號: PIC16F84A-04I/SO
廠商: Microchip Technology
文件頁數(shù): 67/81頁
文件大?。?/td> 0K
描述: IC MCU FLASH 1KX14 EE 18SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 42
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 638 (CN2011-ZH PDF)
配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
I3-DB16F84A-ND - BOARD DAUGHTER ICEPIC3
309-1075-ND - ADAPTER 18-SOIC TO 18-SOIC
309-1011-ND - ADAPTER 18-SOIC TO 18-DIP
309-1010-ND - ADAPTER 18-SOIC TO 18-DIP
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
2001 Microchip Technology Inc.
DS35007B-page 5
PIC16F84A
2.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC16F84A.
These are the program memory and the data memory.
Each block has its own bus, so that access to each
block can occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is,
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 3.0.
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
2.1
Program Memory Organization
The PIC16FXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16F84A, the first 1K x 14 (0000h-03FFh) are
physically implemented (Figure 2-1). Accessing a loca-
tion above the physically implemented address will
cause a wraparound. For example, for locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h,
the instruction will be the same.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK - PIC16F84A
PC<12:0>
Stack Level 1
Stack Level 8
RESET Vector
Peripheral Interrupt Vector
Us
er
M
e
mor
y
Sp
ac
e
CALL, RETURN
RETFIE, RETLW
13
0000h
0004h
1FFFh
3FFh
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