參數(shù)資料
型號: PIC16F84A-04/P
廠商: Microchip Technology
文件頁數(shù): 2/81頁
文件大?。?/td> 0K
描述: IC MCU FLASH 1KX14 EE 18DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 638 (CN2011-ZH PDF)
配用: I3-DB16F84A-ND - BOARD DAUGHTER ICEPIC3
DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
PIC16F84A
DS35007B-page 8
2001 Microchip Technology Inc.
2.3.1
STATUS REGISTER
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bit for
data memory.
As with any register, the STATUS register can be the
destination for any instruction. If the STATUS register is
the destination for an instruction that affects the Z, DC
or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to device logic.
Furthermore, the TO and PD bits are not writable.
Therefore, the result of an instruction with the STATUS
register as destination may be different than intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
Only the BCF, BSF, SWAPF and MOVWF instructions
should be used to alter the STATUS register (Table 7-2),
because these instructions do not affect any status bit.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16F84A and
should be programmed as cleared. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
3: When
the
STATUS
register
is
the
destination for an instruction that affects
the Z, DC or C bits, then the write to these
three bits is disabled. The specified bit(s)
will be updated according to device logic
R/W-0
R-1
R/W-x
IRP
RP1
RP0
TO
PD
ZDC
C
bit 7
bit 0
bit 7-6
Unimplemented: Maintain as ‘0’
bit 5
RP0: Register Bank Select bits (used for direct addressing)
01
= Bank 1 (80h - FFh)
00
= Bank 0 (00h - 7Fh)
bit 4
TO: Time-out bit
1
= After power-up, CLRWDT instruction, or SLEEP instruction
0
= A WDT time-out occurred
bit 3
PD: Power-down bit
1
= After power-up or by the CLRWDT instruction
0
= By execution of the SLEEP instruction
bit 2
Z: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity
is reversed)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, the polarity is
reversed)
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result occurred
Note:
A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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