參數(shù)資料
型號(hào): PIC16F83
廠商: Microchip Technology Inc.
英文描述: 8-Bit CMOS Flash/EEPROM Microcontollrs(每個(gè)I/O口有20mA吸收,25mA驅(qū)動(dòng),64字節(jié)數(shù)據(jù)EEPROM,2.0V的微控制器)
中文描述: 8位CMOS閃存/ EEPROM Microcontollrs(每個(gè)的I / O口有20mA的吸收,25mA電流驅(qū)動(dòng),64字節(jié)數(shù)據(jù)的EEPROM,2.0伏的微控制器)
文件頁數(shù): 42/120頁
文件大?。?/td> 764K
代理商: PIC16F83
PIC16F8X
DS30430A-page 42
1996 Microchip Technology Inc.
8.3
Reset
The PIC16F8X differentiates between various kinds
of reset:
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (during normal operation)
WDT Wake-up (during SLEEP)
Figure 8-8 shows a simplified block diagram of the
on-chip reset circuit. The MCLR reset path has a noise
filter to ignore small pulses. The electrical specifica-
tions state the pulse width requirements for the MCLR
pin.
Some registers are not affected in any reset condition;
their status is unknown on a POR reset and unchanged
in any other reset. Most other registers are reset to a
“reset state” on POR, MCLR or WDT reset during
normal operation and on MCLR reset during SLEEP.
They are not affected by a WDT reset during SLEEP,
since this reset is viewed as the resumption of normal
operation.
Table 8-3 gives a description of reset conditions for the
program counter (PC) and the STATUS register.
Table 8-4 gives a full description of reset states for all
registers.
The TO and PD bits are set or cleared differently in dif-
ferent reset situations (Section 8.7). These bits are
used in software to determine the nature of the reset.
FIGURE 8-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
Reset
MCLR
V
DD
OSC1/
CLKIN
WDT
Module
V
DD
rise
detect
OST/PWRT
On-chip
RC OSC
(1)
WDT
Time_Out
Reset
Power_on_Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Enable OST
Enable PWRT
SLEEP
Note 1:
This is a separate oscillator from the
RC oscillator of the CLKIN pin.
See Table 8-5
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