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鍨嬭櫉(h脿o)锛� PIC16F785-E/SS
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 200/206闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC PIC MCU FLASH 2KX14 20SSOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 67
绯诲垪锛� PIC® 16F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
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绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
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RAM 瀹归噺锛� 128 x 8
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鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
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鍖呰锛� 绠′欢
閰嶇敤锛� XLT20SS1-1-ND - SOCKET TRANSITION 20DIP 20SSOP
AC162060-ND - HEADER INTRFC MPLAB ICD2 20PIN
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93
8272E鈥揂VR鈥�04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
15. 8-bit Timer/Counter0 with PWM
15.1
Features
Two independent output compare units
Double buffered output compare registers
Clear timer on compare match (auto reload)
Glitch free, phase correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency generator
Three independent interrupt sources (TOV0, OCF0A, and OCF0B)
15.2
Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 15-1. For the actual
placement of I/O pins, see 鈥漃in configurations鈥� on page 2. CPU accessible I/O Registers, includ-
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
Figure 15-1. 8-bit Timer/Counter block diagram.
15.2.1
Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
Clock Select
Timer/Counter
DA
T
A
B
U
S
OCRnA
OCRnB
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
=
Fixed
TOP
Value
Control Logic
= 0
TOP
BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TCCRnA
TCCRnB
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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