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參數(shù)資料
| 型號： | PIC16F74T-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 66/104頁 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 4KX14 A/D 44TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus |
| 標(biāo)準(zhǔn)包裝： | 1,200 |
| 系列： | PIC® 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 33 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 帶卷 (TR) |
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Micrel, Inc.
KSZ8851-16MLLJ
March 2010
56
M9999-030210-1.0
Transmit Status Register (0x72 – 0x73): TXSR
This register keeps the status of the last transmitted frame.
Bit
Default Value
R/W
Description
15-14
0x0
RO
Reserved.
13
0x0
RO
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
12
0x0
RO
TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
11-6
-
RO
Reserved.
5-0
-
RO
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this
register belongs to the frame with this ID.
Receive Control Register 1 (0x74 – 0x75): RXCR1
This register holds control information programmed by the CPU to control the receive function.
Bit
Default Value
R/W
Description
15
0x0
RW
FRXQ Flush Receive Queue
When this bit is set, The receive queue memory is cleared and RX frame pointer is reset.
Note: Disable the RXE receive enable bit[0] first before set this bit, then clear this bit to
normal operation.
14
0x0
RW
RXUDPFCC Receive UDP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct UDP checksum for incoming UDP
frames. Any received UDP frames with incorrect checksum will be discarded.
13
0x0
RW
RXTCPFCC Receive TCP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct TCP checksum for incoming TCP
frames. Any received TCP frames with incorrect checksum will be discarded.
12
0x0
RW
RXIPFCC Receive IP Frame Checksum Check Enable
When this bit is set, the KSZ8851 will check for correct IP header checksum for incoming
IP frames. Any received IP frames with incorrect checksum will be discarded.
11
0x1
RW
RXPAFMA Receive Physical Address Filtering with MAC Address Enable
When this bit is set, this bit enables the RX function to receive physical address that pass
the MAC address filtering mechanism (see Address Filtering Scheme in Table 3 for
detail).
10
0x0
RW
RXFCE Receive Flow Control Enable
When this bit is set and the KSZ8851-16MLLJ is in full-duplex mode, flow control is
enabled, and the KSZ8851-16MLLJ will acknowledge a PAUSE frame from the receive
interface; i.e., the outgoing packets are pending in the transmit buffer until the PAUSE
frame control timer expires. This field has no meaning in half-duplex mode and should be
programmed to 0.
When this bit is cleared, flow control is not enabled.
9
0x0
RW
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue.
When this bit is cleared, all CRC error frames are discarded.
8
0x0
RW
RXMAFMA Receive Multicast Address Filtering with MAC Address Enable
When this bit is set, this bit enables the RX function to receive multicast address that pass
the MAC address filtering mechanism (see Address Filtering Scheme in Table 3 for
detail).
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