參數(shù)資料
型號： PIC16F73-I/SS
廠商： Microchip Technology
文件頁數(shù)： 22/104頁
文件大?。?/td> 0K
描述： IC MCU FLASH 4KX14 A/D 28SSOP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 47
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： 閃存
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 640 (CN2011-ZH PDF)
配用： AC164307-ND - MODULE SKT FOR PM3 28SSOP
2009 Microchip Technology Inc.
DS39682E-page 171
PIC18F45J10 FAMILY
16.4.4
CLOCK STRETCHING
Both 7-Bit and 10-Bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit (SSPxCON2<0>) allows clock stretching
to be enabled during receives. Setting SEN will cause
the SCLx pin to be held low at the end of each data
receive sequence.
16.4.4.1
Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPxCON1 register is
automatically cleared, forcing the SCLx output to be
held low. The CKP being cleared to ‘0’ will assert the
SCLx line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCLx line low, the user has time to service the ISR
and read the contents of the SSPxBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
16.4.4.2
Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPxADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
16.4.4.3
Clock Stretching for 7-Bit Slave
Transmit Mode
The 7-Bit Slave Transmit mode implements clock
stretching by clearing the CKP bit after the falling edge
of the ninth clock, if the BF bit is clear. This occurs
regardless of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCLx line
low, the user has time to service the ISR and load the
contents of the SSPxBUF before the master device
can
initiate
another
transmit
sequence
(see
16.4.4.4
Clock Stretching for 10-Bit Slave
Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-Bit Slave Transmit mode (see Figure 16-11).
Note 1:
If the user reads the contents of the
SSPxBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2:
The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note:
If the user polls the UA bit and clears it by
updating the SSPxADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPxBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
Note 1:
If the user loads the contents of
SSPxBUF, setting the BF bit before the
falling edge of the ninth clock, the CKP bit
will not be cleared and clock stretching
will not occur.
2:
The CKP bit can be set in software
regardless of the state of the BF bit.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC16F73T-E/SO 功能描述:8位微控制器 -MCU 7KB 192 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F73T-E/SS 功能描述:8位微控制器 -MCU 7KB 192 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F73T-E/SSVAO 制造商:Microchip Technology Inc 功能描述:
PIC16F73T-I/ML 功能描述:8位微控制器 -MCU 7KB 192 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F73T-I/SO 功能描述:8位微控制器 -MCU 7KB 192 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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