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參數(shù)資料
| 型號： | PIC16F689 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology |
| 中文描述： | 20引腳閃存的基礎(chǔ)上，8位CMOS微控制器與納瓦技術(shù) |
| 文件頁數(shù)： | 212/294頁 |
| 文件大?。?/td> | 2877K |
| 代理商： | PIC16F689 |
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PIC16F631/677/685/687/689/690
DS41262D-page 210
2007 Microchip Technology Inc.
14.6
Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEP
instruction.
If the Watchdog Timer is enabled:
WDT will be cleared but keeps running.
PD bit in the STATUS register is cleared.
TO bit is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before
SLEEP
was executed (driving high, low or high-
impedance).
For lowest current consumption in this mode, all I/O pins
should be either at V
DD
or V
SS
, with no external circuitry
drawing current from the I/O pin and the comparators
and CV
REF
should be disabled. I/O pins that are high-
impedance inputs should be pulled high or low externally
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at V
DD
or V
SS
for lowest
current consumption. The contribution from on-chip pull-
ups on PORTA should be considered.
The MCLR pin must be at a logic high level.
14.6.1
The device can wake-up from Sleep through one of the
following events:
1.
External Reset input on MCLR pin.
2.
Watchdog Timer Wake-up (if WDT was enabled).
3.
Interrupt from RA2/INT pin, PORTA change or a
peripheral interrupt.
The first event will cause a device Reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT Wake-up occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2.
ECCP Capture mode interrupt.
3.
A/D conversion (when A/D clock source is FRC).
4.
EEPROM write operation completion.
5.
Comparator output changes state.
6.
Interrupt-on-change.
7.
External Interrupt from INT pin.
8.
EUSART Break detect, I
2
C slave.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
WAKE-UP FROM SLEEP
When the
SLEEP
instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the
SLEEP
instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the
SLEEP
instruction, then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following
SLEEP
is not desirable, the
user should have a
NOP
after the
SLEEP
instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
14.6.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If the interrupt occurs
before
the execution of a
SLEEP
instruction, the
SLEEP
instruction will
complete as a
NOP
. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
If the interrupt occurs
during or after
the execu-
tion of a
SLEEP
instruction, the device will imme-
diately wake-up from Sleep. The
SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP
instruction, it may be possible for flag bits to
become set before the
SLEEP
instruction completes. To
determine whether a
SLEEP
instruction executed, test
the PD bit. If the PD bit is set, the
SLEEP
instruction
was executed as a
NOP
.
To ensure that the WDT is cleared, a
CLRWDT
instruction
should be executed before a
SLEEP
instruction.
WAKE-UP USING INTERRUPTS
Note:
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding
interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP
instruction is completely executed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC16F689-E/ML | 功能描述:8位微控制器 -MCU 7.1 KB 256 RAM 18I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC16F689-E/P | 功能描述:8位微控制器 -MCU 7KB 256 RAM 12 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC16F689-E/SO | 功能描述:8位微控制器 -MCU 7KB FL 256R 18 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC16F689-E/SS | 功能描述:8位微控制器 -MCU 7KB FL 256R 18 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC16F689-I/ML | 功能描述:8位微控制器 -MCU 7.1 KB 256 RAM 18I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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