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  • 參數(shù)資料
    型號: PIC16F639-I/SS
    廠商: Microchip Technology
    文件頁數(shù): 27/74頁
    文件大?。?/td> 0K
    描述: IC MCU FLASH 2KX14 20SSOP
    產(chǎn)品培訓模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標準包裝: 67
    系列: PIC® 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 20MHz
    外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,WDT
    輸入/輸出數(shù): 11
    程序存儲器容量: 3.5KB(2K x 14)
    程序存儲器類型: 閃存
    RAM 容量: 128 x 8
    電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
    包裝: 管件
    產(chǎn)品目錄頁面: 638 (CN2011-ZH PDF)
    配用: XLT20SS1-1-ND - SOCKET TRANSITION 20DIP 20SSOP
    XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP
    AC162066-ND - HEADER INTRFC MPLAB ICD2 20PIN
    AC164307-ND - MODULE SKT FOR PM3 28SSOP
    Micrel, Inc.
    KSZ8841-PMQL
    October 2007
    33
    M9999-100407-1.5
    Bit
    Default
    Description
    Provides interrupt line routing information. The basic input/output system
    (BIOS) writes the routing information into to this field when it initialized and
    configures the system. The value in this field indicates which input of the
    system interrupt controller is connected to the K8841P’s interrupt pin. The
    driver can use this information to determine priority and vector information.
    Values in this field are system architecture specific.
    The following table shows the access rules of the register.
    Category
    Description
    Value after hardware reset
    0x281401XX
    Capabilities ID Register (CCID Offset 50H)
    The CCID register is a read-only register that provides information on the KSZ8841-PMQL power management
    capabilities. The following table shows the CCID register bit fields. The CCID register bits [31-16] are mirrored with
    PMCR register bits [15-0].
    Bit
    Default
    Description
    31
    0
    PME Support D3 (cold)
    If this bit is set, the KSZ8841-PMQL asserts PME in D3(cold) power state.
    Otherwise,
    the KSZ8841-PMQL does not assert PME in D3(cold).
    The value of this bit is loaded from the PME_D3_cold bit in the EEPROM.
    30
    1
    PME Support D3 (hot)
    The value of this bit is 1, indicating that the KSZ8841-PMQL may assert
    PME in
    D3(hot) power state.
    29
    0
    PME Support D2
    If this bit is set, the KSZ8841-PMQL asserts PME in D2 power state.
    Otherwise, the
    KSZ8841-PMQL does not assert PME in D2 state.
    The value of this bit is loaded from the PME_D2 bit in the EEPROM.
    28
    0
    PME Support D1
    If this bit is set, the KSZ8841-PMQL asserts PME in D1 power state.
    Otherwise, the
    KSZ8841-PMQL does not assert PME in D1 state.
    The value of this bit loaded from the PME_D1 bit in the EEPROM.
    27
    0
    PME Support D0
    1
    The value of this bit is 0, indicating that the KSZ8841-PMQL does not
    assert PME in
    D0 power state.
    26
    0
    D2 Support
    If this bit is set, it indicates that the KSZ8841-PMQL support D2 power
    state.
    The value of this bit is loaded from the D2_SUP bit in the EEPROM.
    1 References to D0, D1, D2, and D3 are power management states defined in a similar fashion to the way they are defined for PCI.
    For more information, refer to the PCI specification at www.pcisig.com/specifications/conventional/pcipm1.2.pdf.
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