參數(shù)資料
型號: PIC16F630-I/SL
廠商: Microchip Technology
文件頁數(shù): 58/132頁
文件大?。?/td> 0K
描述: IC MCU FLASH 1KX14 EEPROM 14SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 57
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 638 (CN2011-ZH PDF)
2010 Microchip Technology Inc.
DS40039F-page 31
PIC16F630/676
4.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figure 4-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
4.1
Timer0 Operation
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin RA2/T0CKI. The incrementing edge is determined
by
the
source
edge
(T0SE)
control
bit
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
4.2
Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit. The interrupt can be masked
by clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from Sleep since the timer is shut-
off during Sleep.
FIGURE 4-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Note:
Additional information on the Timer0
module is available in the PIC Mid-Range
Reference Manual, (DS33023).
Note:
Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the PIC
Mid-Range
Reference
Manual,
(DS33023).
T0CKI
T0SE
pin
CLKOUT
TMR0
Watchdog
Timer
WDT
Time-out
PS0 - PS2
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
0
1
0
1
0
1
SYNC 2
Cycles
8
8-bit
Prescaler
0
1
(= FOSC/4)
PSA
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