參數(shù)資料
型號(hào): PIC16F628A-I/SS
廠商: Microchip Technology
文件頁(yè)數(shù): 108/180頁(yè)
文件大?。?/td> 0K
描述: IC MCU FLASH 2KX14 EEPROM 20SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 67
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 638 (CN2011-ZH PDF)
配用: XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP
I3DBF648-ND - BOARD DAUGHTER ICEPIC3
AC164307-ND - MODULE SKT FOR PM3 28SSOP
AC162053-ND - HEADER INTERFACE ICD,ICD2 18DIP
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2009 Microchip Technology Inc.
DS40044G-page 33
PIC16F627A/628A/648A
5.0
I/O PORTS
The PIC16F627A/628A/648A have two ports, PORTA
and PORTB. Some pins for these I/O ports are
multiplexed with alternate functions for the peripheral
features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general
purpose I/O pin.
5.1
PORTA and TRISA Registers
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. RA5(1) is a Schmitt Trigger
input only and has no output drivers. All other RA port
pins have Schmitt Trigger input levels and full CMOS
output drivers. All pins have data direction bits (TRIS
registers) which can configure these pins as input or
output.
A ‘1’ in the TRISA register puts the corresponding
output driver in a High-impedance mode. A ‘0’ in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(Comparator Control register) register and the VRCON
(Voltage Reference Control register) register. When
selected as a comparator input, these pins will read
as ‘0’s.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high-impedance output. The user must configure
TRISA<2> bit as an input and use high-impedance
loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
INITIALIZING PORTA
FIGURE 5-1:
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
Note 1:
RA5 shares function with VPP. When VPP
voltage levels are applied to RA5, the
device will enter Programming mode.
2:
On Reset, the TRISA register is set to all
inputs. The digital inputs (RA<3:0>) are
disabled and the comparator inputs are
forced to ground to reduce current
consumption.
3:
TRISA<6:7> is overridden by oscillator
configuration. When PORTA<6:7> is
overridden, the data reads ‘0’ and the
TRISA<6:7> bits are ignored.
CLRF
PORTA
;Initialize PORTA by
;setting
;output data latches
MOVLW
0x07
;Turn comparators off and
MOVWF
CMCON
;enable pins for I/O
;functions
BCF
STATUS, RP1
BSF
STATUS, RP0 ;Select Bank1
MOVLW
0x1F
;Value used to initialize
;data direction
MOVWF
TRISA
;Set RA<4:0> as inputs
;TRISA<5> always
;read as ‘1’.
;TRISA<7:6>
;depend on oscillator
;mode
Data
Bus
Q
D
Q
CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
I/O Pin
Q
D
Q
CK
Input Mode
D
Q
EN
To Comparator
Schmitt Trigger
Input Buffer
VDD
VSS
TRISA
(CMCON Reg.)
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