參數(shù)資料
型號: PIC16F627-04E/P
廠商: Microchip Technology
文件頁數(shù): 91/170頁
文件大?。?/td> 0K
描述: IC MCU FLASH 1KX14 18-DIP
標準包裝: 25
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
配用: DVA16XP183-ND - ADAPTER ICE 18DIP/SOIC/SSOP
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 25
PIC16F62X
3.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 3-3 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0>
→ PCH). The lower exam-
ple in the figure shows how the PC is loaded during a
CALL
or GOTO instruction (PCLATH<4:3>
→ PCH).
FIGURE 3-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
3.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read” (AN556).
3.3.2
STACK
The PIC16F62X family has an 8-level deep x 13-bit
wide hardware stack (Figure 3-1 and Figure 3-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN,
RETLW
or a
RETFIE
instruction execution. PCLATH is not affected
by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
3.4
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register actu-
ally accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no-
operation (although STATUS bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 3-4.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 3-1.
EXAMPLE 3-1:
Indirect Addressing
movlw
0x20
;initialize pointer
movwf
FSR
;to RAM
NEXT
clrf
INDF
;clear INDF register
incf
FSR
;inc pointer
btfss
FSR,4
;all done?
goto
NEXT
;no clear next
;yes continue
PC
12
8
7
0
5
PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12
11 10
0
11
PCLATH<4:3>
PCH
PCL
87
2
PCLATH
PCH
PCL
PCL as
Destination
Note 1: There are no STATUS bits to indicate
stack
overflow
or
stack
underflow
conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL,
RETURN,
RETLW
and RETFIE
instructions, or the vectoring to an
interrupt address.
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