參數(shù)資料
型號： PIC16F526-I/P
廠商： Microchip Technology
文件頁數(shù)： 103/122頁
文件大小： 0K
描述： IC PIC MCU FLASH 1KX12 14DIP
標準包裝： 30
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 11
程序存儲器容量： 1.5KB（1K x 12）
程序存儲器類型： 閃存
RAM 容量： 67 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 14-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 638 (CN2011-ZH PDF)
配用： AC162096-ND - HEADER MPLAB ICD2 PIC16F526 8/14
2009 Microchip Technology Inc.
DS39689F-page 81
PIC18F2221/2321/4221/4321 FAMILY
REGISTER 7-1:
EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write-only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
normal operation, or an improper write attempt)
0 = The write operation completed
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
bit 2
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase/write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
S = Bit can be set by software, but not cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
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