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  • 參數(shù)資料
    型號(hào): PIC16F1826-E/P
    廠商: Microchip Technology
    文件頁(yè)數(shù): 7/109頁(yè)
    文件大小: 0K
    描述: MCU PIC 8BIT 2K FLASH 18-DIP
    標(biāo)準(zhǔn)包裝: 25
    系列: PIC® XLP™ mTouch™ 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 32MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 16
    程序存儲(chǔ)器容量: 3.5KB(2K x 14)
    程序存儲(chǔ)器類型: 閃存
    EEPROM 大?。?/td> 256 x 8
    RAM 容量: 256 x 8
    電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 125°C
    封裝/外殼: 18-DIP(0.300",7.62mm)
    包裝: 管件
    2011 Microchip Technology Inc.
    DS41391D-page 15
    PIC16(L)F1826/27
    2.0
    ENHANCED MID-RANGE CPU
    This family of devices contain an enhanced mid-range
    8-bit CPU core. The CPU has 49 instructions. Interrupt
    capability includes automatic context saving. The
    hardware stack is 16 levels deep and has Overflow and
    Underflow Reset capability. Direct, Indirect, and
    Relative addressing modes are available. Two File
    Select Registers (FSRs) provide the ability to read
    program and data memory.
    Automatic Interrupt Context Saving
    16-level Stack with Overflow and Underflow
    File Select Registers
    Instruction Set
    2.1
    Automatic Interrupt Context
    Saving
    During interrupts, certain registers are automatically
    saved in shadow registers and restored when returning
    from the interrupt. This saves stack space and user
    for more information.
    2.2
    16-level Stack with Overflow and
    Underflow
    These devices have an external stack memory 15 bits
    wide and 16 words deep. A Stack Overflow or Under-
    flow will set the appropriate bit (STKOVF or STKUNF)
    in the PCON register, and if enabled will cause a soft-
    ware Reset. See section Section 3.4 “Stack” for more
    details.
    2.3
    File Select Registers
    There are two 16-bit File Select Registers (FSR). FSRs
    can access all file registers and program memory,
    which allows one Data Pointer for all memory. When an
    FSR points to program memory, there is one additional
    instruction cycle in instructions using INDF to allow the
    data to be fetched. General purpose memory can now
    also be addressed linearly, providing the ability to
    access contiguous data larger than 80 bytes. There are
    also new instructions to support the FSRs. See
    for more details.
    2.4
    Instruction Set
    There are 49 instructions for the enhanced mid-range
    CPU to support the features of the CPU. See
    for more
    details.
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