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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC16F1823-E/ML
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 81/109闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� MCU 8BIT 8K FLASH 16QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 91
绯诲垪锛� PIC® XLP™ 16F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 32MHz
閫i€氭€э細 I²C锛孡IN锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 12
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 3.5KB锛�2K x 14锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 256 x 8
RAM 瀹归噺锛� 128 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 16-VQFN 瑁搁湶鐒婄洡
鍖呰锛� 绠′欢
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�鐣�(d膩ng)鍓嶇81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�
2010-2012 Microchip Technology Inc.
DS41413C-page 33
PIC12(L)F1822/PIC16(L)F1823
Bank 2
100h(1)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
101h(1)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
102h(1)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
103h(1)
STATUS
鈥�
鈥擳O
PD
ZDC
C
---1 1000 ---q quuu
104h(1)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
105h(1)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
106h(1)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
107h(1)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
108h(1)
BSR
鈥�
BSR<4:0>
---0 0000 ---0 0000
109h(1)
WREG
Working Register
0000 0000 uuuu uuuu
10Ah(1)
PCLATH
鈥�
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
10Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 000x 0000 000u
10Ch
LATA
鈥�
鈥擫ATA5
LATA4
鈥擫ATA2
LATA1
LATA0
--xx -xxx --uu -uuu
10Dh
鈥�
Unimplemented
鈥�
10Eh
LATC(2)
鈥�
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
--xx xxxx --uu uuuu
10Fh
鈥�
Unimplemented
鈥�
110h
鈥�
Unimplemented
鈥�
111h
CM1CON0
C1ON
C1OUT
C1OE
C1POL
鈥�
C1SP
C1HYS
C1SYNC 0000 -100 0000 -100
112h
CM1CON1
C1INTP
C1INTN
C1PCH<1:0>
鈥�
C1NCH1(2) C1NCH0
0000 ---0 0000 ---0
113h
CM2CON0(2)
C2ON
C2OUT
C2OE
C2POL
鈥�
C2SP
C2HYS
C2SYNC 0000 -100 0000 -100
114h
CM2CON1(2)
C2INTP
C2INTN
C2PCH<1:0>
鈥�
C2NCH<1:0>
0000 --00 0000 --00
115h
CMOUT
鈥�
鈥擬C2OUT(2) MC1OUT ---- --00 ---- --00
116h
BORCON
SBOREN
鈥�
BORRDY 1--- ---q u--- ---u
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
0q00 0000 0q00 0000
118h
DACCON0
DACEN
DACLPS
DACOE
鈥�
DACPSS<1:0>
鈥�
000- 00-- 000- 00--
119h
DACCON1
鈥�
DACR<4:0>
---0 0000 ---0 0000
11Ah
SRCON0
SRLEN
SRCLK<2:0>
SRQEN
SRNQEN
SRPS
SRPR
0000 0000 0000 0000
11Bh
SRCON1
SRSPE
SRSCKE
SRSC2E(2)
SRSC1E
SRRPE
SRRCKE
SRRC2E
(2)
SRRC1E 0000 0000 0000 0000
11Ch
鈥�
Unimplemented
鈥�
11Dh
APFCON
RXDTSEL
SDOSEL
SSSEL
---
T1GSEL
TXCKSEL
P1BSEL
CCP1SEL 000- 0000 000- 0000
11Eh
鈥�
Unimplemented
鈥�
11Fh
鈥�
Unimplemented
鈥�
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
These registers can be addressed from any bank.
2:
PIC16(L)F1823 only.
3:
Unimplemented. Read as 鈥�1鈥�.
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