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參數(shù)資料
| 型號(hào)： | PIC16F1508-I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 54/123頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 7KB FLASH 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 38 |
| 系列： | PIC® XLP™ 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲(chǔ)器容量： | 7KB（4K x 14） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x10b，D/A 1x5b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 管件 |
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Micrel, Inc.
KSZ8873MLLJ
September 2011
36
M9999-091911-1.8
All the packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the “AND”
feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed to be “receive sniff”, port 2 is programmed
to be “transmit sniff”, and port 3 is programmed to be the “sniffer port”. A packet received on port 1 is destined to
port 2 after the internal lookup. The KSZ8873MLLJ forwards the packet to both port 2 and port 3.
Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer port”.
All these per port features can be selected through registers 17, 33 and 49 for ports 1, 2 and 3, respectively.
Rate Limiting Support
The KSZ8873MLLJ provides a fine resolution hardware rate limiting from 64Kbps to 99Mbps. The rate step is 64Kbps
when the rate range is from 64Kbps to 960Kbps and 1Mbps for 1Mbps to 100Mbps(100BT) or to 10Mbps(10BT) (refer to
Data Rate Limit Table). The rate limit is independently on the “receive side” and on the “transmit side” on a per port basis.
For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the data receive rate for
each priority at each port can be limited by setting up Ingress Rate Control Registers. On the transmit side, the data
transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control Registers. The size of
each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte, in addition to the data field (from
packet DA to FCS).
For ingress rate limiting, KSZ8873MLLJ provides options to selectively choose frames from all types, multicast, broadcast,
and flooded unicast frames. The KSZ8873MLLJ counts the data rate from those selected type of frames. Packets are
dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter
frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each output
priority queue is limited by the egress rate specified.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the
ingress end, and may be therefore slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded in
the static table, it is also not learned in the dynamic MAC table. The KSZ8873MLLJ is then configured with the option to
either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register 14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in
applications such as voice over Internet Protocol (VoIP).
Configuration Interface
The KSZ8873MLLJ can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8873MLLJ is typically programmed using an EEPROM. If no EEPROM is present, the
KSZ8873MLLJ is configured using its default register settings. Some default settings are configured via strap-in pin
options. The strap-in pins are indicated in the “Pin Description and I/O Assignment” table.
I
2C Master Serial Bus Configuration
With an additional I
2C (“2-wire”) EEPROM, the KSZ8873MLLJ can perform more advanced switch features like “broadcast
storm protection” and “rate control” without the need of an external processor.
For KSZ8873MLLJ I
2C Master configuration, the EEPROM stores the configuration data for register 0 to register 120 (as
defined in the KSZ8873MLLJ register map) with the exception of the “Read Only” status registers. After the de-assertion
of reset, the KSZ8873MLLJ sequentially reads in the configuration data for all control registers, starting from register 0.
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