參數(shù)資料
型號: PIC16CR74-I/L
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 92/172頁
文件大?。?/td> 2964K
代理商: PIC16CR74-I/L
PIC16CR7X
DS21993C-page 24
2007 Microchip Technology Inc.
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt.
2.2.2.7
PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt.
REGISTER 2-6:
PIE2: (ADDRESS 8Dh)
U-0
R/W-0
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented: Read as ‘0’
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1
= Enables the CCP2 interrupt
0
= Disables the CCP2 interrupt
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-7:
PIR2: (ADDRESS 0Dh)
U-0
R/W-0
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented: Read as ‘0’
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare mode:
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM mode:
Unused
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