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    參數(shù)資料
    

    


    


    
型號(hào)：
PIC16CE624-04/SO

    

    
廠商：
Microchip Technology

    

    
文件頁(yè)數(shù)：
8/100頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC MCU OTP 1KX14 EE COMP 18SOIC

    

    
產(chǎn)品培訓(xùn)模塊：
Asynchronous Stimulus
    
	8-bit PIC® Microcontroller Portfolio
    		

    

    
標(biāo)準(zhǔn)包裝：
42

    

    
系列：
PIC® 16C

    

    
核心處理器：
PIC
    		

    

    
芯體尺寸：
8-位
    		

    

    
速度：
4MHz
    		

    

    
外圍設(shè)備：
欠壓檢測(cè)/復(fù)位，POR，WDT
    		

    

    
輸入/輸出數(shù)：
13
    		

    

    
程序存儲(chǔ)器容量：
1.75KB（1K x 14）
    		

    

    
程序存儲(chǔ)器類型：
OTP
    		

    

    
EEPROM 大?。?/td>
128 x 8
    		

    

    
RAM 容量：
96 x 8
    		

    

    
電壓 - 電源 (Vcc/Vdd)：
3 V ~ 5.5 V
    		

    

    
振蕩器型：
外部
    		

    

    
工作溫度：
0°C ~ 70°C
    		

    

    
封裝/外殼：
18-SOIC（0.295"，7.50mm 寬）
    		

    

    
包裝：
管件
    		

    

    

    

	
    
    
    

    
    
	
     2010 Microchip Technology Inc.
    DS39935C-page 105
    ENC424J600/624J600
    11.0 FLOW CONTROL
    Flow control provides a mechanism for network
    stations to temporarily stop transmission of data to
    themselves. This feature is commonly used to prevent
    buffer overruns while receiving data.
    ENC424J600/624J600 devices are capable of both
    automatic and manual flow control. The hardware can
    advertise when it is temporarily unable to receive data
    and delay transmissions when a remote system does
    the same. Flow control is supported for both full and
    half-duplex links. It can either be initiated manually by
    software, or configured to enable automatically when
    insufficient space remains in the receive buffer
    memory.
    Flow control operation is configured by the FCOP<1:0>
    bits (ECON1<7:6>), the AUTOFC bit (ECON2<7>), the
    RXPAUS and PASSALL bits (MACON1<2:1>), and the
    EPAUS and ERXWM registers in some modes.
    11.1
    Modes of Operation
    Flow control operation differs between full and
    half-duplex links. Both modes are supported, but it is
    important to understand the difference before enabling
    flow control in an application.
    11.1.1
    HALF-DUPLEX MODE
    When the link is operating in Half-Duplex mode, flow
    control operates by jamming the network. The node
    wishing to inhibit transmissions to itself sends a
    preamble pattern of alternating ones and zeros (55h)
    on the medium; this is also known as asserting back
    pressure on the link. Since the link is operating under
    Half-Duplex mode, all connected nodes must wait
    before transmitting. If a node does transmit, compliant
    nodes will detect the collision and wait until the
    jamming stops to retransmit. This effectively jams the
    network until flow control is disabled.
    If a frame is to be transmitted while flow control is
    enabled, the ENCX24J600 will stop jamming, wait the
    standard Inter-Packet Gap (IPG) delay, then attempt to
    transmit. Because all traffic was previously jammed,
    several nodes may begin transmitting and several
    collisions may occur. The hardware will transmit and
    resume jamming as soon as possible, but it is feasible
    for other nodes to transmit packets before this
    happens. This limitation of flow control in half-duplex
    operation cannot be avoided.
    Given the detrimental effect that back pressure based
    flow control inflicts on a network, along with the
    possible lack of effectiveness, it is recommended that
    flow control be avoided in Half-Duplex mode unless the
    application is used in a closed network environment
    with proper testing.
    When operating in Half-Duplex mode, setting
    FCOP<1:0> to ‘00’ disables the flow control. Any other
    combination enables flow control and causes the
    device to jam the network.
    11.1.2
    FULL-DUPLEX MODE
    Flow control for full-duplex links is much more robust.
    Instead of jamming the network, a station can send a
    pause control frame to the remote system. The pause
    frame is directed to a special Multicast destination
    address (01-08-C2-00-00-01) and indicates how long
    the remote node should wait before transmitting again.
    This time is expressed in units of pause quanta, where
    one pause quanta is equal to 512 bit times.
    While a station is silenced or paused, reception is still
    enabled. If another pause control frame arrives, any
    previous value is discarded and the timer restarts using
    the new pause time value. If the received control frame
    has a timer value of zero, the pause is terminated and
    transmission resumes immediately.
    When operating in Full-Duplex mode, each combina-
    tion of FCOP<1:0> has a different effect on transmitting
    control frames. These combinations are discussed in
    11.1.3
    TRANSMITTING AND RECEIVING
    PAUSE CONTROL FRAMES
    The ENCX24J600 automatically processes incoming
    pause control frames without application intervention.
    When a pause control frame is received, the MAC
    internally sets the pause timer. Transmission is inhib-
    ited while the timer is active. If an application attempts
    to transmit a packet during this time, the transmission
    logic will stall until the time expires (i.e., TXRTS will
    stay set for longer than normal).
    Pause control frames are normally filtered out by the
    MAC and are not written to the receive buffer. Setting the
    PASSALL bit (MACON1<1>) alters this behavior and
    causes these frames to pass through the receive filters.
    If the frame is accepted, it will be written to the receive
    buffer. However, setting PASSALL will also cause the
    MAC to not process the pause control frame. The trans-
    mission logic will allow immediate transmission without
    regard to the remote pause requests.
    Before using either automatic or manual flow control,
    set the pause time value with the EPAUS register. This
    value controls the pause time value that is transmitted
    with each pause control frame. Each unit of pause
    quanta in this register is equal to 512 bit times.
    Note:
    Flow control is an optional portion of the
    IEEE 802.3 specification and may not be
    implemented on all remote devices.
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

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PIC16CE624-20/P
功能描述:8位微控制器 -MCU 1.75KB 96 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
PIC16CE624-20/SO
功能描述:8位微控制器 -MCU 1.75KB 96 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
PIC16CE624-20/SS
功能描述:8位微控制器 -MCU 1.75KB 96 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
PIC16CE624-20E/P
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PIC16CE624-20E/SO
功能描述:8位微控制器 -MCU 1.75KB 96 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT

    

    
    
    
    
	
    	
    
    
     
     
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