參數(shù)資料
型號: PIC16C924T-08I/L
廠商: Microchip Technology
文件頁數(shù): 109/115頁
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 LCD DVR 68PLCC
標準包裝: 300
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
連通性: I²C,SPI
外圍設備: LCD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 帶卷 (TR)
配用: AC164308-ND - MODULE SKT FOR PM3 68PLCC
DVA16XL680-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164024-ND - ADAPTER PICSTART PLUS 68PLCC
Micrel, Inc.
KSZ8873MLL/FLL/RLL
September 20, 2013
93
Revision 1.6
VLAN Table
The KSZ8873 uses the VLAN table to perform look ups. If 802.1Q VLAN mode is enabled (register 5, bit 7 = 1), this table
will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID
(filter ID), VID (VLAN ID), and VLAN membership as described in Table 17.
Table 17. Format of Static VLAN Table (16 Entries)
Bit
Name
R/W
Description
Default
19
Valid
R/W
= 1, entry is valid
= 0, entry is invalid
1
18-16
Membership
R/W
Specify which ports are members of the VLAN. If
a DA lookup fails (no match in both static and
dynamic tables), the packet associated with this
VLAN will be forwarded to ports specified in this
field. For example, 101 means port 3 and 1 are in
this VLAN.
111
15-12
FID
R/W
Filter ID. KSZ8873 supports 16 active VLANs
represented by these four bit fields. FID is the
mapped ID. If 802.1Q VLAN is enabled, the look
up will be based on FID+DA and FID+SA.
0x0
11-0
VID
R/W
IEEE 802.1Q 12 bits VLAN ID
0x001
If 802.1Q VLAN mode is enabled, KSZ8873 will assign a VID to every ingress packet. If the packet is untagged or tagged
with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non-null
VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the
packet will be dropped and no address learning will take place. If the VID is valid, the FID is retrieved. The FID+DA and
FID+SA lookups are performed. The FID+DA look up determines the forwarding ports. If FID+DA fails, the packet will be
broadcast to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA will be learned.
Examples:
1.
VLAN Table Read (Read the 3
rd Entry)
Write to reg. 121 (0x79) with 0x14
// Read VLAN table selected
Write to reg. 122 (0x7A) with 0x02
// Trigger the read operation
Then,
Read reg. 129 (0x81), VLAN table bits [19:16]
Read reg. 130 (0x82), VLAN table bits [15:8]
Read reg. 131 (0x83), VLAN table bits [7:0]
2.
VLAN Table Write (Write the 7
th Entry)
Write to reg. 129 (0x81), VLAN table bits [19:16]
Write to reg. 130 (0x82), VLAN table bits [15:8]
Write to reg. 131 (0x83), VLAN table bits [7:0]
Write to reg. 121 (0x79) with 0x04
// Write VLAN table selected
Write to reg. 122 (0x7A) with 0x06
// Trigger the write operation
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