The A/D conversion time per bit i" />
參數(shù)資料
型號: PIC16C924T-08/L
廠商: Microchip Technology
文件頁數(shù): 98/115頁
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 LCD DVR 68PLCC
標準包裝: 300
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
連通性: I²C,SPI
外圍設備: LCD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉換器: A/D 5x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 帶卷 (TR)
配用: AC164308-ND - MODULE SKT FOR PM3 68PLCC
DVA16XL680-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164024-ND - ADAPTER PICSTART PLUS 68PLCC
1997 Microchip Technology Inc.
DS30444E - page 83
PIC16C9XX
12.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is dened as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selected. The four possible options for TAD are:
2TOSC
8TOSC
32TOSC
Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6
s.
Table 12-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
12.3
Conguring Analog Port Pins
The ADCON1 and TRISA registers control the opera-
tion of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, all pins
congured as analog inputs will read as
cleared (a low level). Pins congured as
digital inputs, will convert an analog input.
Analog levels on a digitally congured
input will not affect the conversion accu-
racy.
Note 2: Analog levels on any pin that is dened as
a digital input (including the AN4:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specication.
TABLE 12-1: TAD vs. DEVICE OPERATING FREQUENCIES
A/D Clock Source (TAD)
Device Frequency
Operation
ADCS1:ADCS0
8 MHz
5 MHz
1.25 MHz
333.33 kHz
2TOSC
00
250 ns(2)
400 ns(2)
1.6
s
6
s
8TOSC
01
1
s
1.6
s
6.4
s
24
s(3)
32TOSC
10
4
s
6.4
s
25.6
s(3)
96
s(3)
RC
11
2 - 6
s(1,4)
2 - 6
s(1,4)
2 - 6
s(1,4)
2 - 6
s(1)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4
s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When derived frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
sleep mode only
5: For extended voltage devices (LC), please refer to the electrical specications section.
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