參數(shù)資料
型號: PIC16C765-I/PT
廠商: Microchip Technology
文件頁數(shù): 110/165頁
文件大小: 0K
描述: IC MCU OTP 8KX14 USB 44TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 24MHz
連通性: SCI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: OTP
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.35 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 636 (CN2011-ZH PDF)
配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
AC164020-ND - MODULE SKT PROMATEII 44TQFP
2000 Microchip Technology Inc.
Preliminary
DS41124C-page 49
PIC16C745/765
8.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
The input clock (FINT/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS<1:0>
(T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Register 8-1 shows the Timer2 control register.
Additional information on timer modules is available in
the PICmicro Mid-Range MCU Family Reference
Manual (DS33023).
8.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
a write to the TMR2 register
a write to the T2CON register
any device RESET (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
FIGURE 8-1:
TIMER2 BLOCK DIAGRAM
REGISTER 8-1:
TIMER2 CONTROL REGISTER (T2CON: 12h)
Comparator
TMR2
Sets flag
TMR2 reg
output
RESET
Postscaler
Prescaler
PR2 reg
2
FINT
1:1
1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
to
T2OUTPS<3:0>
T2CKPS<1:0>
U-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0
R
= Readable bit
W= Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6-3:
TOUTPS<3:0>: Timer2 Output Postscale Select bits
0000
= 1:1 Postscale
0001
= 1:2 Postscale
0010
= 1:3 Postscale
1111
= 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1
= Timer2 is on
0
= Timer2 is off
bit 1-0:
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00
= Prescaler is 1
01
= Prescaler is 4
1x
= Prescaler is 16
745cov.book Page 49 Wednesday, August 2, 2000 8:24 AM
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