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2000 Microchip Technology Inc.
DS30605C-page 15
PIC16C63A/65B/73B/74B
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
The PIC16C63A/65B/73B/74B has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. All devices covered by this data sheet
have 4K x 14 bits of program memory. The address
range is 0000h - 0FFFh for all devices.
Accessing a location above 0FFFh will cause a wrap-
around.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
FIGURE 4-1:
PIC16C63A/65B/73B/74B
PROGRAM MEMORY MAP
AND STACK
4.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
RP1:RP0 (STATUS<6:5>)
= 00
→ Bank0
= 01
→ Bank1
= 10
→ Bank2
= 11
→ Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
All implemented banks contain SFRs. Frequently used
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
4.2.1
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly, or indi-
rectly,
through
the
File
Select
Register
(FSR)
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
Stack Level 1
Stack Level 8
RESET Vector
Interrupt Vector
On-chip Program
Memory (Page 1)
Memory (Page 0)
CALL,RETURN
RETFIE,RETLW
Use
rMe
mo
ry
Sp
a
c
e
Note:
Maintain the IRP and RP1 bits clear in
these devices.