參數(shù)資料
型號： PIC16C73A-20/SP
廠商： Microchip Technology
文件頁數(shù)： 94/114頁
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 A/D PWM 28DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 15
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
PIC16C7X
DS30390E-page 80
1997 Microchip Technology Inc.
11.2.1
OPERATION OF SSP MODULE IN SPI
MODE
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
Serial Data Out (SDO)
Serial Data In (SDI)
Serial Clock (SCK)
Additionally a fourth pin may be used when in a slave
mode of operation:
Slave Select (SS)
When initializing the SPI, several options need to be
specied. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specied:
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Output/Input data on the Rising/
Falling edge of SCK)
Clock Rate (Master mode only)
Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb rst. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the Buffer Full bit, BF (SSPSTAT<0>)
and ag bit SSPIF are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>) will be
set. User software must clear bit WCOL so that it can
be determined if the following write(s) to the SSPBUF
completed successfully. When the application software
is expecting to receive valid data, the SSPBUF register
should be read before the next byte of data to transfer
is written to the SSPBUF register. The Buffer Full bit BF
(SSPSTAT<0>) indicates when the SSPBUF register
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the SSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF register must be read and/or writ-
ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col-
lision does not occur. Example 11-1 shows the loading
of the SSPBUF (SSPSR) register for data transmission.
The shaded instruction is only required if the received
data is meaningful.
Applicable Devices
72 73 73A 74 74A 76 77
EXAMPLE 11-1: LOADING THE SSPBUF
(SSPSR) REGISTER
The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR register is
not directly readable or writable, and can only be
accessed from addressing the SSPBUF register. Addi-
tionally, the SSP status register (SSPSTAT) indicates
the various status conditions.
FIGURE 11-3: SSP BLOCK DIAGRAM
(SPI MODE)
BSF
STATUS, RP0
;Specify Bank 1
LOOP BTFSS SSPSTAT, BF
;Has data been
;received
;(transmit
;complete)?
GOTO
LOOP
;No
BCF
STATUS, RP0
;Specify Bank 0
MOVF
SSPBUF, W
;W reg = contents
;of SSPBUF
MOVWF RXDATA
;Save in user RAM
MOVF
TXDATA, W
;W reg = contents
; of TXDATA
MOVWF SSPBUF
;New data to xmit
Read
Write
Internal
data bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0
shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
Applicable Devices
72 73 73A 74 74A 76 77
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