參數資料
型號： PIC16C73A-10/SP
廠商： Microchip Technology
文件頁數： 97/114頁
文件大小： 0K
描述： IC MCU OTP 4KX14 A/D PWM 28DIP
產品培訓模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 15
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數： 22
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數據轉換器： A/D 5x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
其它名稱： PIC16C73A-10/SPR
PIC16C73A-10/SPR-ND
1997 Microchip Technology Inc.
DS30390E-page 83
PIC16C7X
11.3
SPI Mode for PIC16C76/77
This section contains register denitions and opera-
tional characteristics of the SPI module on the
PIC16C76 and PIC16C77 only.
FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C76/77)
R/W-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit7
bit0
bit 7:
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
bit 6:
CKE: SPI Clock Edge Select (Figure 11-11, Figure 11-12, and Figure 11-13)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is
detected last, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
detected last, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Applicable Devices
72 73 73A 74 74A 76 77
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