1995 Microchip Technology Inc.
DS30390B-page 299
PIC16C7X
WDT .................................................................................129
Block Diagram ..........................................................137
Period .......................................................................137
Programming Considerations ..................................137
Timeout ....................................................................129
WDTE bit ..........................................................................122
Word ................................................................................122
WR pin ...............................................................................54
X
XMIT_MODE ......................................................................92
XORLW Instruction ..........................................................152
XORWF Instruction ..........................................................152
Z
Z bit ....................................................................................30
Zero bit .................................................................................9
LIST OF EXAMPLES
Example 3-1:
Example 4-1:
Instruction Pipeline Flow...........................20
Call of a Subroutine in Page 1 from
Page 0......................................................42
Indirect Addressing...................................42
Initializing PORTA ....................................43
Initializing PORTB ...................................45
Initializing PORTC....................................47
Read-Modify-Write Instructions on an
I/O Port.....................................................53
Changing Prescaler (Timer0
Changing Prescaler (WDT
Reading a 16-bit Free-Running Timer......67
Changing Between Capture Prescalers ...73
Loading the SSPBUF (SSPSR)
Register....................................................79
Calculating Baud Rate Error.....................95
Equation 13-1: A/D Minimum Charging Time .................114
Example 13-1:
Calculating the Minimum Required
Sample Time ..........................................114
Example 13-2:
Doing an A/D Conversion
(PIC16C70/71/71A)................................116
Example 13-3:
Doing an A/D Conversion
(PIC16C72/73/73A/74/74A)....................116
Example 13-4:
4-bit vs. 8-bit Conversion Times.............117
Example 14-1:
Saving STATUS and W Registers in RAM
(PIC16C70/71/71A)................................136
Example 14-2:
Saving STATUS and W Registers in RAM
(PIC16C72/73/73A/74/74A)....................136
LIST OF FIGURES
Example 4-2:
Example 5-1:
Example 5-2:
Example 5-3:
Example 5-4:
Example 7-1:
Example 7-2:
Example 8-1:
Example 10-1:
Example 11-1:
→
Timer0)........63
WDT)........63
→
Example 12-1:
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 3-5:
Figure 4-1:
PIC16C70/71/71A Block Diagram.............10
PIC16C72 Block Diagram.........................11
PIC16C73/73A Block Diagram..................12
PIC16C74/74A Block Diagram..................13
Clock/Instruction Cycle..............................20
PIC16C70 Program Memory Map and
Stack.........................................................21
PIC16C71/71A Program Memory Map
and Stack..................................................21
PIC16C72 Program Memory Map and
Stack.........................................................22
PIC16C73/73A/74/74A Program Memory
Map and Stack..........................................22
PIC16C70/71 Register File Map ...............23
PIC16C71A Register File Map..................23
PIC16C72 Register File Map ....................24
PIC16C73/73A/74/74A Register File
Map...........................................................24
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 4-9:
Figure 4-10:
Figure 4-11:
Status Register (Address 03h, 83h)...........30
OPTION Register (Address 81h)...............31
INTCON Register for PIC16C70/71/71A
(Address 0Bh, 8Bh) ...................................32
INTCON Register for PIC16C72/73/
73A/74/74A (Address 0Bh, 8Bh)................33
PIE1 Register PIC16C72 (Address 8Ch)...34
PIE1 Register PIC16C73/73A/74/74A
(Address 8Ch)............................................35
PIR1 Register PIC16C72 (Address 0Ch)...36
PIR1 Register PIC16C73/73A/74/74A
(Address 0Ch)............................................37
PIE2 Register (Address 8Dh) ....................38
PIR2 Register (Address 0Dh)....................39
PCON Register (Address 8Eh)..................40
Loading of PC In Different Situations.........41
Direct/Indirect Addressing..........................42
Block Diagram of RA3:RA0 and RA5 Pins 43
Block Diagram of RA4/T0CKI Pin..............44
Block Diagram of RB3:RB0 Pins ...............45
Block Diagram of RB7:RB4 Pins ...............45
PORTC Block Diagram (Peripheral Output
Override)....................................................47
PORTD Block Diagram (in I/O Port Mode)49
TRISE Register (Address 89h)..................51
PORTE Block Diagram (in I/O Port Mode) 52
Successive I/O Operation..........................53
PORTD and PORTE Block Diagram
(Parallel Slave Port)...................................54
Timer0 Block Diagram...............................59
Timer0 Timing: Internal Clock/No
Prescale.....................................................59
Timer0 Timing: Internal Clock/
Prescale 1:2...............................................60
Timer0 Interrupt Timing .............................60
Timer0 Timing with External Clock............61
Block Diagram of the Timer0/WDT
Prescaler....................................................62
T1CON: Timer1 Control Register
(Address 10h)............................................65
Timer1 Block Diagram...............................66
Timer2 Block Diagram...............................69
T2CON: Timer2 Control Register
(Address 12h)............................................70
CCP1CON Register (Address 17h)/
CCP2CON Register (Address 1Dh)...........72
Capture Mode Operation Block Diagram...73
Compare Mode Operation Block Diagram.73
Simplified PWM Block Diagram.................74
SSPSTAT: Sync Serial Port Status Register
(Address 94h)............................................77
SSPCON: Sync Serial Port Control Register
(Address 14h)............................................78
SSP Block Diagram (SPI Mode)................79
SPI Master/Slave Connection....................80
SPI Mode Timing (Master Mode or Slave
Mode w/o SS Control)................................81
SPI Mode Timing (Slave Mode with
SS Control)................................................81
Start and Stop Conditions..........................83
7-bit Address Format.................................84
I
C 10-bit Address Format.........................84
Slave-Receiver Acknowledge....................84
Data Transfer Wait State...........................84
Master-transmitter Sequence ....................85
Master-receiver Sequence.........................85
Figure 4-12:
Figure 4-13:
Figure 4-14:
Figure 4-15:
Figure 4-16:
Figure 4-17:
Figure 4-18:
Figure 4-19:
Figure 4-20:
Figure 4-21:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 5-7:
Figure 5-8:
Figure 5-9:
Figure 5-10:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 8-1:
Figure 8-2:
Figure 9-1:
Figure 9-2:
Figure 10-1:
Figure 10-2:
Figure 10-3:
Figure 10-4:
Figure 11-1:
Figure 11-2:
Figure 11-3:
Figure 11-4:
Figure 11-5:
Figure 11-6:
Figure 11-7:
Figure 11-8:
Figure 11-9:
Figure 11-10:
Figure 11-11:
Figure 11-12:
Figure 11-13:
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